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Automotive Chip Design
EV Powertrain Electronics
Long-cycle design programs where IP, foundry, and ecosystem partnerships execute against tapeout and market windows.
Infineon
NXP
Texas Instruments
STMicroelectronics
Inside this journey
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Pre-Discovery
Align the room on outcomes, decision process, and constraints before deeper discovery.
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Stakeholder Alignment
Confirm decision roles, timelines, and qualification gates for component selection across powertrain, controls, safety, and procurement.
Alignment Questions
Quick Orientation: Your Project in One Breath
- Please give the project name, vehicle program (or platform), your title, and the primary contact for technical decisions.
- Where are you in the decision lifecycle for powertrain semiconductors?
- What is your target production start window (month/year) and the rolling qualification timeline you expect?
- Who on your team will be directly responsible for component qualification sign-off (names or roles)?
- Briefly describe one past component selection (or rejection) that shaped how you approach supplier evaluation today.
Are We Aligned or Just Guessing About Who Decides?
- Tell us about the single biggest assumption your team is making about the decision process that might be wrong.
- Which stakeholders must explicitly approve semiconductor selection for this program?
- How do procurement and sourcing influence technical decisions—do they set hard constraints or negotiate after technical selection?
- What formal qualification gates exist (e.g., design review, EMI sign-off, functional-safety evidence) and which gate typically causes the most delay?
- If someone pushed back on schedule today, which single decision would you change to keep momentum?
Where This Design Keeps You Up at Night
- If you had to name the one technical risk that would derail the program, what is it—and why does it feel so threatening?
- Which failure modes from past inverters/OBC/BMS integrations worry you most right now?
- How often do you see thermal constraints force derating or software limits in your designs, and what percentage of power is typically affected?
- Tell us about a recent verification failure—what failed, how long did it take to root-cause, and what was the emotional / program impact?
- Which supplier-provided artifacts have been weakest for you historically (e.g., thermal models, EMC debug guides, ISO 26262 evidence)?
What If Integration Risk Vanished—What Would You Build?
- If integration risk were no longer a constraint, what higher-level vehicle or system capability would you pursue that you currently aren’t?
- What are your target system-level KPIs we should design toward (pick all that apply and prioritize in the next question)?
- Rank the top three KPIs from the previous question in order of importance for this program.
- What absolute numbers are you targeting (e.g., inverter efficiency 98.2% at 25°C, thermal headroom +20°C at continuous current)? Please list the metric and the target.
- How would meeting those targets change your product roadmap, cost position, or competitive edge?
What Would Success Look Like at the Testbench and in the Field?
- Describe the single go/no-go acceptance criterion you cannot compromise on for semiconductor selection (e.g., ISO 26262 artifact with traceable SPICE-based failure mode analysis).
- Which qualification tests must pass before you commit to a production design?
- What pass/fail thresholds do you apply for each critical test (give numeric thresholds where possible)?
- Who signs off test results and artifacts for each domain (thermal, EMC, functional safety, controls), and who ultimately owns the risk if something fails in production?
- If a component fails one critical test mid-qualification, what is your preferred recovery path?
Where Our Support Could Shift the Odds in Your Favor
- Imagine your vendor could guarantee one thing that would materially reduce your schedule risk—what would that guarantee be?
- Which types of supplier support do you value most during qualification?
- How quickly do you expect vendor support responses during qualification phases (SLAs)?
- What sample commitment cadence and quantity do you need to keep your timelines intact (prototypes, engineering runs, pre-production)?
- Are there proprietary or IP constraints that would limit how much supplier engineers can interact with your code or system-level data? If so, describe.
The Practical Roadmap — Who Does What, When?
- What is the single biggest operational blocker that has delayed past qualifications (e.g., lab availability, sample lead time, decision ambiguity)?
- List the three milestone dates you need to hit in the next 12–18 months (e.g., prototype delivery, EMC window, safety artifact submission).
- Which owners on your side will need recurring checkpoints with our application team (roles only)?
- What lab resources or test fixtures do you already have, and what will you expect the supplier to provide?
- If we propose a 6–8 week co-development sprint, what measurable outcomes would convince you it was worth it?
Commit or Pause: What’s the Next Small Decision?
- Given everything above, what is the smallest, low-risk action we can take together in the next two weeks to build momentum?
- What concerns would make you hesitate to take that next action right now?
- What would you need from our commercial or sample commitments to feel comfortable moving forward?
- How would you like us to package the follow-up: a technical packet, a joint plan with milestones, or a supplier statement of support?
- Finally, how soon can your team confirm a date for the first collaborative session (provide a preferred week or range)?
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Current State Mapping
Document existing inverter, OBC, and BMS architectures, failure modes, thermal constraints, and verification status to expose integration risks.
Current State
Quick Snapshot: Your Powertrain Blueprint
- Which of these subsystems are in scope for this vehicle program right now?
- Please describe the high-level electrical architecture for the subsystems above (topology, isolated vs. non-isolated domains, major power rails).
- What nominal and peak battery voltages does the system target?
- Which project phase best describes where you are today?
- Who are the primary decision owners we should engage for architecture, controls, functional safety, and procurement?
- Which power semiconductor technologies are you planning to use in the power stage?
Where the Smoke Shows Up First
- What single failure mode—or late discovery—keeps your engineering team awake at night when you think about inverter/OBC/BMS integration?
- How often has that failure mode occurred in past programs or prototypes?
- When that issue has shown up, what was the root cause as you understand it (design, thermal, EMC, software control, supplier part variability, manufacturing)?
- What is the typical impact when it occurs (program delay, rework, field recall, performance degradation)?
- What mitigation actions have you tried and with what result? Please include who owned the mitigation and whether it fully resolved the issue.
- How confident are you in your failure-mode detection during bench validation versus in-vehicle testing?
Thermals: Confessions from the Heat Sink
- Have you been counting on thermal margin to be the easiest problem—and if so, where has that assumption broken down?
- What cooling approach do you use for power modules and associated electronics?
- What steady-state and transient thermal limits are driving your design (case/PCB/junction temps, allowed duty cycles)?
- At typical peak-load scenarios, what percentage of your thermal budget is consumed by the power stage vs. control electronics?
- Have you observed thermal derating, throttling, or lifetime-accelerating temperature cycles in tests or field data?
- What thermal modeling or empirical data (CFD, board-level thermal pictures, IR logs) can you share to help us assess integration risk?
Integration Blind Spots We Don't Talk About
- What integration problem has surprised you the most late in a program—and why do you think it slipped through earlier reviews?
- Which electrical and mechanical interfaces are highest risk for integration (signal isolation, ground strategy, connector pinouts, harness routing, creepage/clearance)?
- Which communications and control protocols between devices are in use and how mature are the software stacks?
- What is the current status of system-level integration testing (bench harness tests, HIL, in-vehicle validation)?
- Where do you see the largest gap between component-level verification and system-level verification?
- Who on your team owns end-to-end integration testing and escalation when cross-domain issues appear?
Safety and Verification: Is the Checklist Real or Ritual?
- Is ISO 26262 guiding your architecture decisions or simply documenting choices after the fact—and what evidence makes you say that?
- What ASIL targets apply to key functions in scope (traction inverter gate control, pre-charge, contactor control, BMS cell balancing)?
- Which safety artifacts are available today (FMEDA, FTA, safety concept, software architecture, verification plan)?
- Where are the biggest evidence gaps that could block ISO 26262 sign-off?
- What level of silicon-level diagnostics and fault coverage do you expect from gate drivers, MCUs, and PMICs?
- What is your current timeline for completing safety verification and getting the safety case to a reviewable state?
Supplier Reality Check: Parts, Samples, and Timing
- If a supplier sample delay pushed your test schedule, what downstream impact would you expect (qualification shift, lost launch, budget overrun)?
- What is the lead time and current availability for critical semiconductor components you're evaluating?
- Which components are already qualified to AEC standards in your BOM versus which are still vendor-qualified?
- Do you have contractual or procurement constraints (preferred vendors, single-source parts, long lead commitments) that limit swap options during qualification?
- What customs, regulatory, or logistics issues have affected sample shipping or lab availability in past programs?
What Would Let You Sleep Better?
- If you could guarantee one measurable metric at launch (efficiency, thermal margin, MTBF, ASIL evidence), which single metric would change the boardroom conversation?
- What success signals would you expect to see during a 12–18 month qualification program to feel confident about production readiness?
- Which types of support would most de-risk your path to those metrics (select up to three)?
- What timeline would you consider acceptable for running an initial integrated hardware/software validation (from sample receipt to first-integration results)?
- On an emotional level, how would you describe the team’s confidence about meeting launch targets today?
Next Steps — How We Partner to Close the Gaps
- If we could remove your single highest-risk unknown in 30 days, what would you want us to resolve and why would that matter?
- Who from your team will be the integration owner(s) and the functional-safety contact for collaborative work?
- What artifacts and data can you commit to sharing early to accelerate our joint assessment (schematics, layout, thermal logs, EMI scans, safety requirements)?
- Do you have an NDA, export control, or IP guardrail we need to align on before exchanging detailed designs?
- What cadence and format of collaboration works best for you (weekly technical sync, on-site lab sessions, shared ticket tracker, single POC)?
- What would success look like at the end of our first 90 days working together (specific deliverables or milestones)?
- Are there any immediate blockers we should know about (funding freeze, hiring gaps, lab access, supplier holds)?
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Outcome Discovery
Define target system-level outcomes (efficiency, thermal headroom, ISO 26262 objectives), success signals, and the 12–18 month qualification milestones.
Discovery Questions
Quick Orientation — What's Top of Mind?
- What's the single highest-priority outcome for your next traction inverter / OBC / BMS program?
- What is the program or platform name (or a short descriptor we should use in all coordination)?
- What's the nominal and peak battery voltage domain we'll be designing for?
- Roughly where are you in the calendar relative to production intent—when does qualification need to be complete?
- Who owns component selection across powerstage, controls, safety, and procurement in your org? (select all that apply)
- Which existing reference designs or incumbent suppliers are you currently using as your baseline?
If We Don't Fix It, What Blows Up?
- If we miss the real integration risk now, where will it blow up—performance, thermal, safety, schedule, or something else?
- Describe the top three integration risks you currently worry about (be specific: component, interface, duty-cycle, or failure mode).
- Which failure modes have you actually seen in prototypes or early builds? (select all that apply)
- How aligned are your lab verification results with your models—do thermal and EMC models under- or over-predict real behavior?
- Which test or verification activities are incomplete today and most likely to expose a late surprise?
- How long have these risks existed and what workaround are you tolerating today (impact to performance, warranty exposure, or schedule)?
Why Have You Kept Doing It This Way?
- What's the single biggest reason you haven't moved to a higher-efficiency or newer power-stage approach (e.g., SiC) yet?
- Which long-held assumptions in your program most influence component selection (e.g., 'supplier handles FMEDA', 'we control thermal design', 'procurement requires X price')?
- How often do procurement or OEM-approved vendor lists force design compromises you don't want?
- If you had to relax one procedural constraint to accelerate qualification by 3–6 months, what would that be?
- Who in your organization pushes hardest for innovation vs who pushes hardest for minimal program risk? Name role(s) and brief stance.
If Success Is Defined in the Boardroom, What Will It Look Like?
- List the 3–5 measurable system-level KPIs that will determine program success and include target values/units where possible (e.g., efficiency %, junction temp margin, fault-rate thresholds).
- Which ISO 26262 ASIL objectives must be demonstrable for this program to proceed to production?
- What absolute efficiency improvement (or loss) would be considered meaningful for the powerstage in your system—express as % points or W/W if possible.
- What thermal headroom or margin do you require under sustained high-load duty cycles (describe as ΔT, junction vs ambient, or allowable derating)?
- Which qualification milestones must be achieved in the 12–18 month window? (select all that apply)
- What are the 'quick success signals' during qualification that would make you comfortable escalating approval (e.g., first-pass sample, signed FMEDA, EMC pass)?
Who Needs to Be Satisfied — and How Will You Know?
- Who holds veto power on component selection and final supplier approval if a single criterion fails?
- Which stakeholders must sign off before production commitment? (select all that apply)
- For each critical stakeholder, what evidence convinces them (brief mapping: stakeholder → required artifact or metric)?
- Are there hard commercial thresholds that will veto a supplier (unit cost, NRE cap, long-term pricing guarantees)?
- When trade-offs are required, how do you prioritize functional safety artifacts versus thermal and efficiency targets?
Where Could Our Tech Move the Needle?
- Which of our product categories are you most interested in exploring to solve your primary risks? (select all that apply)
- Give one concrete scenario (power, switching freq, topology, duty cycle) where incremental efficiency or thermal margin would change your program decision.
- Are you targeting silicon, silicon-carbide, or a hybrid power stage for this program?
- What component-level ASIL support or safety artifacts would accelerate your safety case (select all that apply)?
- Which application-engineering services would most de-risk integration (select up to three)?
- If we could commit to a specific sample + support plan within a defined lead-time, what lead-times would be acceptable for you?
What Would Stop the Deal Even If Everything Else Looks Good?
- What single missing artifact or assurance would stop your qualification dead even if all tests passed?
- Which non-technical blockers worry you most about new semiconductor suppliers? (select all that apply)
- Describe any prior supplier interactions that undermined trust or caused late delays—what specifically happened and how was it resolved (if at all)?
- Which test facilities or resources are scarce for your program and most likely to bottleneck qualification?
- Do you require pre-approved vendor lists or specific compliance certifications (AEC, ISO audits) we must meet? If yes, list them.
- What contingency approach do you prefer if a critical component fails late in qualification?
If We Showed a 12–18 Month Plan, What Makes You Pull the Trigger?
- How ready are you to engage on a joint qualification plan right now?
- What would an ideal mutual commitment include (deliverables, sample counts, timelines, support SLAs)—please be specific where possible.
- Which acceptance criteria do you want explicitly written into a mutual commitment to avoid ambiguity?
- Who should be the named owners on your side for samples, test coordination, and safety artifacts? (select all that apply)
- What cadence of checkpoints would you prefer during the 12–18 month qualification (to maintain momentum and transparency)?
- What outstanding technical or commercial questions absolutely must be answered before you will sign a mutual commit?
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Solution Experience
Translate the customer’s scenarios into a tangible plan showing how our gate drivers, MCUs, PMICs and reference designs deliver required efficiency, thermal margins, and ASIL support.
Experience Meetings
- Solution Experience Prep & Current State Validation
- Customer Scenario Walkthrough — Efficiency & Thermal Mapping
- Reference Design Proof — Targeted Efficiency & ASIL Demonstration
- Integration Risks, Verification Responsibilities & Qualification Timeline
- Final Validation Alignment & Sign-off on Solution Plan
- Lock sample delivery commitments and the 12–18 month qualification timeline with explicit gates.
- Seller: Produce a one-page verification checklist mapping each acceptance criterion to a proof activity.
- Brief Recap of Claimed Outcomes
- Provide demonstrable proof that the reference design meets the Future State for the selected scenario.
- Validate that ASIL-required diagnostics and response times are achievable with the proposed components.
- Force the customer's explicit confirmation that the proof addresses their consequence.
- Seller: Share detailed simulation files, test logs, thermal maps, and measurement setups used in the proof.
- Customer: Provide validation response — confirm whether proof resolves the stated consequence for this scenario and list any remaining concerns.
- Both: Identify any follow-up proofs (additional scenarios, HW-in-loop) and owners.
- Review Verification Master Plan (VMP) Overview
- Agree a concrete VMP with owners, labs, and dates covering EMC, thermal, reliability, and functional-safety verification.
- Establish a shared risk register with mitigation owners and deadlines.
- Introductions & Meeting Objectives
- Seller: Deliver the editable Verification Master Plan and risk register within 3 business days for sign-off.
- Customer: Confirm internal approvers and any mandatory third-party lab constraints.
- Both: Agree sample delivery dates and initial lab bookings; update calendar invites.
- Consolidated Solution Plan Walkthrough
- Obtain explicit customer confirmation that the Solution Plan demonstrates the Future State and removes the stated consequence.
- Secure signed commitment (or agreed next-step sign-off path) for sample delivery and VMP execution.
- Assign owners and deadlines for the first 90 days of verification activities.
- Both: Sign or formally acknowledge the Solution Plan (digital sign-off or email) within agreed timeframe.
- Seller: Trigger sample build and shipment per the agreed schedule and share tracking.
- Customer: Confirm lab bookings and internal resource allocation for the verification kickoff.
- Establish a single-sentence Current State that all parties agree is accurate.
- Quantify the business/technical consequence of the Current State in measurable terms.
- Agree a one-sentence Future State outcome that proofs must demonstrate.
- Confirm required artifacts and owners for the scenario proofs.
- Customer: Provide validated BOM, duty-cycles, thermal maps, failure summaries, and safety targets within 3 business days.
- Seller: Prepare initial gap checklist and simulation plan tailored to provided artifacts.
- Both: Confirm participants and date for Scenario Walkthrough meeting.
- Recap Current/Future State & Objectives
- Translate customer scenarios into numeric device-level targets for efficiency and losses.
- Define thermal headroom requirements and identify hot-spots needing mitigation.
- Agree ASIL support requirements and which device features must be demonstrated.
- Set explicit validation signals and measurable acceptance criteria for subsequent proofs.
- Seller: Run targeted loss simulations for the top 2 prioritized scenarios and deliver charts showing per-device loss contributions.
- Customer: Provide any missing thermal boundary conditions and confirm worst-case ambient and duty durations.
- Ownership & Responsibilities
- Validation Against Current State & Consequence
- One-Sentence Current State
- Review and Prioritize Scenarios
- Efficiency Proof (Sim / Measured)
- Confirm Sample, Support & SLAs
- Explicit Consequence Quantification
- Thermal Proof & Headroom
- Loss Breakdown & Device Mapping
- Risk Register & Mitigations
- Thermal Margin Mapping
- Sample Commitments & Timeline
- Sign-off Actions & Immediate Next Steps
- One-Sentence Future State
- ASIL & Diagnostics Proof
- ASIL / Diagnostics Constraints
- Tying Proof to Consequence & Validation
- Prework & Data Validation
- Decision Gates & Acceptance Sign-offs
- Open Q&A and Final Clarifications
- Define Validation Signals & Acceptance Criteria
- Alignment on Next Meeting Scope
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Solution Scope
Define included modules (gate drivers, MCU, PMIC, reference designs), sample and support commitments, verification responsibilities, and measurable acceptance criteria.
Scope Configuration
- Supply AEC-Q100/AEC-Q101 qualified isolated gate drivers
- Supply high-voltage power management ICs (up to 800V)
- Supply motor control microcontrollers with FOC firmware bundle
- Supply battery management front-end ICs with active balancing
- Deliver SiC traction inverter reference design (schematics & PCB)
- Deliver onboard charger reference design (schematics & PCB)
- Deliver battery management system reference design (hardware & firmware)
- Provide gate driver evaluation kit (board, connectors, load)
- Provide thermal simulation models and enclosure CAD files
- Provide EMC-optimized PCB layout packages and guidelines
- Deliver ISO 26262 ASIL-D safety package (FMEDA, safety manual)
- Provide application firmware integration kit (drivers and examples)
Scope Questions
Supply AEC-Q100/AEC-Q101 qualified isolated gate drivers
- Do you require AEC-Q100/AEC-Q101 qualified isolated gate drivers for this program?
- Target DC bus / nominal voltage class for the gate driver application
- What power semiconductor type(s) will the gate drivers interface with?
- Required insulation / isolation expectations (creepage/clearance, reinforced, basic)
- Which switching performance metrics are acceptance criteria for the gate drivers? (rise/fall times, dV/dt immunity, propagation)
- Who will own verification and qualification of the gate driver in your integration tests?
- Any additional interface constraints (e.g., connector type, footprint, pinout constraints)?
Supply high-voltage power management ICs (up to 800V)
- Do you plan to include our high-voltage power management ICs in the scope of deliverables?
- Which primary functions do you need from HV PMICs?
- Maximum operating voltage and derating expectations for PMICs (confirm up to 800V usage profile)
- What thermal/environmental qualification levels are required (temperature range, thermal cycles)?
- Do you require integrated protection features (OVP, UVLO, OCP, ESD)?
- Who will perform system-level validation of the PMIC behavior (customer, seller, shared)?
- List any certification or production constraints for PMIC sourcing (e.g., single-sourced, long-term supply commitments).
Supply motor control microcontrollers with FOC firmware bundle
- Do you want our motor-control MCU + FOC firmware bundle included in scope?
- Which motor types and topologies must the MCU/FOC bundle support?
- Required control loop performance and sampling rates (e.g., current loop bandwidth, PWM frequency)
- Do you need ASIL-level safety mechanisms or diagnostics integrated into the firmware?
- Will the MCU need to integrate with an existing vehicle network or RTOS (e.g., AUTOSAR, CAN, Ethernet)?
- Who will own motor-control tuning and final parameterization during qualification?
- Any constraints on MCU pinout, package, or thermal dissipation we should account for?
Supply battery management front-end ICs with active balancing
- Should active cell balancing-capable BMS front-end ICs be included?
- Which cell chemistry and cell count range will the BMS support?
- Do you require passive balancing, active balancing, or both?
- What measurement accuracy and sampling cadence are required for SOC/SOH estimation?
- Is functional safety integration required for BMS front-end (e.g., diagnostics for ASIL levels)?
- Who will be responsible for cell-level validation and cycling to establish acceptance criteria?
- Any mechanical or connector constraints for the BMS front-end (stack height, connector family)?
Deliver SiC traction inverter reference design (schematics & PCB)
- Do you want a full SiC traction inverter reference design (schematics + PCB) delivered?
- Which inverter power class and switching topology should the reference design target?
- Target semiconductor base: discrete SiC modules, SiC half-bridge modules, or integrated power stages?
- Do you need thermal management features included in the reference PCB (embedded liquid channels, heat-sink interface)?
- What level of documentation and tooling is required (Gerbers, BOM, assembly notes, test procedures)?
- Who will perform system-level validation of the reference inverter and supply test assets?
- Any constraints on footprint, connector types, or regulatory targets (e.g., HVIL, isolation plan)?
Deliver onboard charger reference design (schematics & PCB)
- Is an onboard charger (OBC) reference design required in scope?
- What AC input and DC output power / voltage ranges must the OBC reference design support?
- Do you require power factor correction and grid-compliance features included?
- Are safety isolation and creepage/clearance specs for OBC mandated by your OEM customer?
- What thermal and enclosure constraints (ambient temp, ingress rating) apply to the OBC?
- Who will certify the OBC for EMC and grid compatibility tests?
- Any preferred topologies or components (e.g., SiC in boost stage, resonant converter)?
Deliver battery management system reference design (hardware & firmware)
- Do you want a complete BMS reference design including both hardware and firmware?
- Which system-level features must the BMS reference support (cell monitoring, SOC estimation, thermal management, contactor control)?
- What functional safety level must the BMS reference be capable of supporting?
- Do you require integration with vehicle cloud or telematics for SOC/SOH reporting?
- What is your expected validation cycle for BMS (cell cycling duration, environmental tests)?
- Who will maintain and adapt the delivered firmware to your ECU environment?
- Any constraints on connectors, harness interfaces, or mechanical mounting we should follow?
Provide gate driver evaluation kit (board, connectors, load)
- Do you want a gate driver evaluation kit included (board, standard connectors, resistive/inductive load)?
- Which evaluation goals are most important (characterize switching, thermal performance, EMI, fault injection)?
- How many evaluation kits are required initially and for qualification stages?
- Do you need bundled test scripts and measurement procedures for the kit?
- Will evaluation be performed in your lab or at our application lab (or both)?
- Any special harness, connector keying, or safety interlocks required for kit delivery?
- Do you require expedited sample delivery or loaner options during development?
Provide thermal simulation models and enclosure CAD files
- Do you require thermal simulation models and enclosure CAD files for system-level analysis?
- What simulation formats are required (e.g., STEP, Parasolid, native CFD tool models)?
- What thermal cases must be modeled (steady-state high-load, repeated duty-cycle, cold-start)?
- Do you require seller-supported thermal validation (test lab correlation) or only model delivery?
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Mutual Commit
Agree commercial terms, sample delivery and qualification schedule, support SLAs, and mutual responsibilities for functional safety artifacts.
Agreement Modules
- Statement of Work (SOW)
- Commercial Terms & Pricing
- Supply Agreement / Purchase Order Terms
- Sample Delivery & Qualification Schedule
- Acceptance Criteria & Qualification Protocol
- Functional Safety Commitments
- Service Level Agreement (SLA) — Application & Escalation
- Documentation & Technical Handover
- Reference Design License & IP Terms
- Change Control & Engineering Change Order (ECO)
- Manufacturing Readiness & Forecasting
- Logistics, Incoterms & Customs
- Payment Terms & Invoicing
- Warranty, Returns & RMA Policy
- Risk Allocation & Indemnification
- Confidentiality & Data Handling Addendum
- Export Compliance & Regulatory Declarations
- Governance & Steering Committee
- Termination, Renewal & Renewal Options
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Deployment
Operationalize sample delivery, lab validation, and production readiness with controls and owners.
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Pre-Deployment Readiness
Confirm sample inventory, test-lab bookings, safety documentation, and owners for EMC, thermal, and functional-safety runs.
Readiness Questions
Start With the Big Picture — Your Program at a Glance
- In one short sentence, how would you describe the vehicle program and the role our components would play?
- Which system are we talking about for this engagement?
- What vehicle segment and expected annual production volume best describe this program?
- Which phase is the program currently in (pick the closest)?
- Who are the core internal stakeholders we should work with (roles rather than names)?
- What would success look like for this initial discovery conversation?
Are There Invisible Constraints That Could Kill Your Schedule?
- If a single overlooked constraint forced a six‑month delay, what would it be?
- Which technical constraints keep you up at night for this build?
- Which components are you most concerned about integrating (pick all that apply)?
- How clearly defined are your pass/fail qualification gates for component selection?
- How long has this program been carrying the constraints you just described?
- Which assumption about the power stage or controls do you suspect might be wrong (e.g., thermal dissipation, switching frequency, sensor latency)?
Where It Burns — Integration, Thermal, and Safety Pain
- When integration fails in your prototypes, who on the team feels the impact most and why?
- What recurring failure modes are you seeing in bench or vehicle tests?
- Which validation areas are currently giving you marginal or failing results?
- What is your current thermal margin for the power electronics under sustained high-load duty (estimate in °C or category)?
- How confident are you in the fidelity of your thermal and EMC models?
- Tell us about the most painful field or RMA issue this program has faced and what it exposed about system fragility.
Who Holds the Keys? Decision Maps That Make or Break Timelines
- If you could get a single stakeholder to sign off tomorrow, who would it be — and why haven’t they signed yet?
- Which roles must approve semiconductor selection before samples are ordered?
- How do you typically trade off performance, safety (ASIL), and unit cost when selecting components?
- What procurement or supplier requirements will we need to meet (audit, qualification, single-source constraints)?
- How long does your internal approval cycle usually take from technical sign-off to purchase order?
- Which stakeholder on your side tends to be the most conservative about adopting new silicon, and what do they need to be convinced?
If This Were Perfect — Targets That Would Make You Proud
- What outcome on this program would feel like a career-defining win for you?
- Which system-level metrics are non-negotiable for you to call the design successful?
- What specific efficiency improvement or loss reduction target do you need versus your incumbent solution?
- Which qualification milestones in the next 12–18 months are critical to hit (pick the ones you’ll measure us against)?
- How will you signal 'acceptance' at each milestone — what artifacts or pass criteria do you require?
- What risk trade-offs would you accept (for example, faster schedule with incremental pieces of safety evidence versus waiting for full FMEDA)?
What Would Make You Confident to Wire Up Our Hardware Right Now?
- What single deliverable would make you stop asking questions and start integrating our silicon this week?
- Which of these pre‑deliverables do you require before placing an initial sample order?
- How many samples and on what schedule do you need for initial integration and qualification?
- Which test resources are currently the gating constraint for your schedule?
- What level and cadence of application-engineering support will make integration low-risk for you?
- What's an absolute red-line blocker that would stop you from testing our samples (e.g., missing ISO 26262 evidence, thermal mounting incompatibility)?
Clear Next Steps — What Keeps Momentum Alive
- If we leave this conversation with one committed action from your side, what must it be to preserve schedule momentum?
- Who should we list as the primary owner on your side for sample validation and scheduling?
- Which checkpoints and cadence work best to keep stakeholders aligned?
- What acceptance criteria must be met to greenlight the component for pre-production (be as specific as possible)?
- Which regulatory or compliance artifacts should we prepare proactively to speed procurement and qualification?
- When is the earliest window you can accept sample shipment and a reserved lab booking for integration tests?
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Deployment Enablement
Coordinate sample shipments, application-engineering tasks, reference-design integration, and sequencing with clear owners and timelines.
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Validation Checklist
Execute qualification tests, capture results against acceptance criteria, and document pass/fail actions required for production approval.
Validation Questions
Starting Point — Tell Us Where You Are
- What's the current program this conversation should map to (product name / platform / vehicle program)?
- Which subsystem(s) are you evaluating right now?
- When do you expect to lock component selection and start PPAP/production trials?
- Who on your team will be most involved in evaluating semiconductor components (titles/roles)?
- How mature is your current electrical architecture documentation (schematics, thermal model, failure mode list)?
What Assumptions Are Slowing You Down?
- Which incumbent assumptions would you be reluctant to revisit when choosing a new gate driver/MCU/PMIC supplier?
- How confident are you that your current assumptions about switching performance and thermal margins match real-world sustained-load conditions?
- Tell us about a time an assumption about a semiconductor component caused a schedule or safety issue—what happened and what did that cost you?
- Which assumption—if proven wrong during qualification—would force a redesign or vendor change?
- What would convince you to actively re-evaluate a long-standing supplier relationship?
Where Hidden Risks Are Lurking
- What integration surprises have derailed past powertrain projects for you?
- Which failure modes keep you awake about deploying new gate drivers or PMICs into an inverter or OBC?
- How complete is your verification traceability today—do you map every safety requirement back to a test and a responsible owner?
- Where do you lack visibility today: hardware stress profiles, software timing margins, or supplier failure data? Please be specific.
- Which of these would be most disruptive if it occurred during your 12–18 month qualification window?
If This Design Must Last 10 Years, What Keeps You Up At Night?
- What single reliability or safety concern would make you halt a supplier selection for production commitment?
- What quantitative thermal margin (°C) do you require between worst-case silicon junction and system thermal limit for long-range continuous operation?
- Which ASIL target is needed for the functions our devices will support in your architecture?
- What qualification milestones in the next 12–18 months would make you comfortable moving from evaluation to production?
- How do you prefer safety evidence to be presented—detailed FMEDA +ASIL mapping, executive summary, or both?
What Tradeoffs Are You Willing to Make?
- Would you accept a 1–2% loss in peak efficiency to gain 20–30% more sustained thermal headroom?
- Rank these priorities for your powertrain electrical choices.
- What maximum increase in BOM cost per vehicle would you accept for a measurable reliability or safety improvement?
- How much schedule slack do you realistically have to validate a new semiconductor across electrical, thermal, and safety domains?
- Which tradeoff conversations would require alignment from your procurement or leadership (short answer: who must sign off)?
Decision Mechanics — Who Signs, When, and Why?
- Who are the decision owners for component selection, and what will each person need to see to sign off?
- What formal gates or qualification milestones does your procurement require before issuing a production purchase order?
- How do you prefer supplier commitments to be documented—MOU, SOW, formal contract addendum, or purchase agreement terms?
- What internal timing or budget cycles constrain when you can award supply contracts?
- Are there specific procurement constraints we should know about (approved vendor list, dual-source requirements, NRE caps)?
If a Supplier Could Remove One Burden, What Would It Be?
- Which single supplier deliverable would most accelerate your evaluation and reduce program risk?
- If you could choose a format for reference artifacts, what do you need most?
- How would you use a supplier-delivered thermal model or test report in your qualification flow?
- What turnaround time on custom application engineering support would materially change your timeline?
- Would hands-on help (lab visits, co-testing) be valuable, and if so, how much on-site time would you expect?
Commitment Signals — Does This Fit Your Roadmap?
- What's the smallest supplier commitment that would materially reduce your perceived risk?
- How many production-like samples would you require for full system-level verification?
- Would you accept staged sample deliveries (preliminary eval parts then production-like parts) or do you need production-like parts from day one?
- Are you open to signing a mutual non-disclosure or a short MOU to accelerate data exchange?
- Which service-level commitments matter most when samples fail qualification (what expect supplier to provide)?
How Will Success Be Measured?
- What top three metrics will leadership use to declare this component selection a success?
- What pass/fail acceptance criteria must the supplier test results meet for you to green-light production?
- How important is independent third-party verification (e.g., accredited lab EMC/thermal) to your final decision?
- If qualification uncovers a minor non-conformance, what remediation path is acceptable (retest, design change, compensating controls)?
- What time window would be considered an acceptable delay before a supplier selection is considered at risk?
Next Steps — What Would Make This Conversation Truly Valuable?
- If we could start tomorrow, what's the one early win you'd want to see in the next 30 days?
- Who should be on a 30-minute follow-up to map responsibilities and immediate actions (names, roles, emails)?
- What's your preferred cadence and format for check-ins during the 12–18 month qualification window?
- What data-sharing formats and tools do you prefer for artifacts (e.g., DOORS/GitLab, Excel traceability, PDF reports, CAD/STEP files)?
- What would cause you to walk away from this vendor conversation entirely?
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Success
Review qualification outcomes, capture lessons learned, and maintain a shared channel for issues, RMAs, and enhancement requests.
Success Reviews
- Qualification Outcomes Review
- Lessons Learned & Continuous Improvement Workshop
- Support, Escalation & RMA Channel Setup
- Enhancement Requests & Roadmap Prioritization
- Customer Success Closeout & Ongoing Review Cadence
Issues & Enhancements
- Schedule engineering deep-dive for any high-effort/high-impact items to refine estimates.
- Update test procedures, safety artifacts, and integration checklists based on agreed changes.
- Create improvement project charters for systemic items and assign project leads.
- Schedule a follow-up review to verify implementation of quick wins.
- Scope & SLA Confirmation
- Establish a shared, accessible channel and operational workflow for issues and RMAs.
- Document SLA targets, evidence required for RMA, and escalation paths.
- Agree monitoring KPIs and reporting cadence to track support health.
- Provision shared channel with initial templates (issue intake, RMA request) and invite lists.
- Publish RMA policy document and triage checklist to the shared channel.
- Configure monitoring dashboard and schedule weekly health reports for the first quarter.
- Confirm and publish on-call roster and escalation contacts.
- Capture Enhancements from Qualification
- Create a prioritized enhancement backlog with clear short-term commitments and roadmap items.
- Align on timelines and communication expectations for customer-facing commitments.
- Ensure critical safety or production-impact items are escalated for immediate action.
- Create enhancement backlog entries in the agreed tracking tool with impact, effort, and owner.
- Opening & Objectives
- Publish a short roadmap update to the customer summarizing commitments and timelines.
- Define re-evaluation cadence for backlog items and assign product owner.
- Summary of Decisions & Open Items
- Formally close the qualification stage with a complete handover package and known owners.
- Establish a measurable KPI set and review cadence to monitor field performance.
- Ensure training, inventory, and commercial follow-ups are scheduled and owned.
- Deliver the closeout packet (reports, safety docs, reference designs) to the shared channel and confirm receipt.
- Schedule the first quarterly business review and recurring health-check meetings.
- Assign Customer Success Manager and document primary contacts and escalation owners.
- Publish agreed KPIs dashboard and set automated reporting to stakeholders.
- Reach a clear, documented decision on production readiness for the qualified configuration.
- Assign corrective action owners with deadlines and re-test triggers.
- Ensure all deviations are traced to acceptance criteria and mitigation plans.
- Publish consolidated qualification report with pass/fail matrix and attach test artifacts.
- Assign RCA leads for each failure and schedule targeted re-test slots.
- Update acceptance criteria or test procedures where gaps were identified.
- Schedule a follow-up decision meeting tied to corrective action milestones.
- Pre-read Metrics & Context
- Produce a vetted list of actionable improvements with owners and timelines.
- Update program artifacts (checklists, test plans, handover templates) to prevent recurrence.
- Establish a short list of high-impact quick wins to implement before the next program phase.
- Publish 'Lessons Learned' document and circulate to stakeholders within 5 business days.
- Handover Package Review
- What Worked Well
- Executive Summary of Results
- Consequence & Customer Impact Assessment
- Shared Channel & Access
- Pass/Fail Matrix Review
- What Didn’t Work / Surprises
- Inventory & Sample Commitments
- RMA Policy, Triage & Evidence Requirements
- Effort & Risk Triage (Rough Sizing)
- Prioritization Using Value vs Effort
- Root Cause Analysis of Failures
- Escalation Matrix & Severity Definitions
- Root Causes & Systemic Issues
- Training & Enablement Plan
- Roadmap Commitments & Communication Plan
- Actionable Improvements & Controls
- Monitoring, Reporting & KPIs
- Risk Assessment & Impact to Production
- Ongoing KPIs & Review Cadence