Set the Scene: Your Program in One Line

• In one sentence, describe the vehicle platform or program driving the move from CAN to a zonal Ethernet backbone.
• How far away is your OEM platform freeze date? Options: < 6 months, 6–9 months, 9–12 months, 12–18 months, > 18 months, Not defined
• Who on your team owns the architectural decision for network silicon (role/title)? Options: Network Architect, Central Electronics Platform, ECU Hardware Lead, Program Manager, Procurement, Other
• Which teams will need to be involved in silicon qualification and sign-off? Options: Network architecture, ECU hardware, Software/AUTOSAR, EMC lab, Safety/ISO 26262, Procurement, Quality/PPAP, Other
• What is the single biggest worry you have right now about this migration?

If Your Network Could Talk — What Would It Tell Us?

• Imagine your current vehicle network could complain — what's the one recurring problem it would name?
• Describe the existing ECU domains and the legacy CAN/CAN FD topology we will be bridging from (number of domains, gateway points, star/linear/bus, etc.).
• Which ECUs are high-risk during migration because they cannot be redesigned quickly or are tied to safety functions? Options: Powertrain ECU(s), ADAS/Domain ECU(s), Body control ECU(s), Infotainment Gateway, Unknown / Need to audit
• Have you observed any intermittent field issues (EMC, latency spikes, sleep-wake failure) that suggest deeper systemic problems? Please describe specific incidents and how often they occur.
• What parts of your current supply base or qualification process have historically caused the most schedule slippage?

When 'Good Enough' Breaks the Program

• If a transceiver or switch fell short on EMC or sleep power after design freeze, what would that realistically force you to do? Options: Board redesign, Add external filtering, Accept reduced margins, Delay program, Switch vendor, Other
• What are your numeric target acceptance criteria today for latency, EMC margins, and sleep-mode current? (If you use ranges, please specify.) Options: Latency (specify in next field), EMC margin (specify in next field), Sleep current (specify in next field)
• Which protocol compliance must be proven in qualification (select all that apply) and which standards are mandatory for this program? Options: AUTOSAR compliance, OPEN Alliance PHY/Link conformance, CAN/CAN FD ISO specs, LIN spec, FlexRay spec, Other
• How do you prioritize those signals of success when trade-offs arise (e.g., slightly higher latency vs. significantly lower sleep power)? Options: Latency first, EMC first, Sleep power first, Protocol compliance prioritized, Balanced trade-offs, Depends by ECU/domain
• Tell us about a past trade-off decision that later caused pain—what was chosen, why, and what happened?

Who Holds the Keys — Roles, Timelines, and What 'Good' Actually Means

• Who ultimately signs off that silicon is acceptable for production for this program, and what authority do they have to pause the program? Options: OEM central electronics lead, Program manager, Tier-1 system integrator, Quality/PPAP authority, Cross-functional steering committee, Undecided
• For each stakeholder (architecture, HW design, EMC lab, procurement), what does ‘good enough’ look like—please list stakeholder and their top 1–2 acceptance criteria.
• What are the qualification lead times you must budget for silicon, and what milestones compress the schedule if accelerated? Options: < 3 months, 3–6 months, 6–9 months, 9–12 months, > 12 months
• If a stakeholder raises a blocking issue during qual, what is your current escalation path and expected SLAs for resolution? Options: Immediate cross-functional war room, Weekly steering call, Issue logged and triaged within program, No formal process
• Who will own on-site lab access, evaluation fixtures, and coordination with our engineering for validation runs? Options: Customer test lab, Tier-1 lab, Third-party lab, We need vendor support

What Would a Failed Integration Actually Cost?

• If an errata forced a board redesign after design lock, estimate the program impact in weeks or cost bands. Options: < 4 weeks / Low cost, 4–8 weeks / Moderate, 8–16 weeks / High, > 16 weeks / Critical
• How comfortable are you with silicon errata that require board-level workarounds versus a full silicon respin? Options: Comfortable with workarounds, Prefer workaround only if minor, Require silicon fix, Undecided
• What level of supply continuity commitment do you require from a silicon supplier (lead-time guarantees, lifetime availability, last-time buy terms)? Options: Formal long-term supply contract, Preferred supplier with forecasts, Spot buys only, Must-have lifetime availability clause
• Describe any contractual or procurement constraints (approved fab lists, country-of-origin restrictions, long-term supplier policies) that we should know.
• How do you measure acceptable risk for a new silicon family on a decade-long vehicle program? Options: Low tolerance, Moderate with mitigation plan, High tolerance if cost savings, Depends on ECU function

Show Me the Evidence — Tests, Fixtures, and What Wins Your Confidence

• What specific evaluation-board data or lab reports would make you say, “We can move forward” (EMC plots, sleep current traces, deterministic latency histograms, protocol conformance logs)? Options: EMC test reports, Sleep current measurements, Latency distributions, Protocol conformance logs, Integration test results, All of the above
• Which validation gates are mandatory before silicon is allowed into your integration lab (select all that apply)? Options: EMC passed, AUTOSAR/OPEN Alliance compliance, Sleep-mode power target met, Latency within spec, Thermal and mechanical tests, Supplier quality audit
• How many physical samples and what test fixture access do you require for your qualification plan (numbers and any special fixtures)? Options: Standard eval board (1–3), Multiple boards + CAN harnesses (4–10), Fleet of prototype ECUs (>10), Need vendor to provide fixtures
• Do you require co-located engineering support during evaluation runs (vendor engineer on-site vs. remote support)? Options: On-site vendor engineer, Remote support + scheduled on-site visits, Remote only, Undecided
• What format and level of traceability do you require for test evidence (raw logs, summarized reports, DFMEA trace to tests)? Options: Raw logs + summary, Pass/fail matrix with traces, Formal report for PPAP, Simple executive summary

What Would Success Feel Like — Commitments, Timelines, and Next Steps

• If this migration is successful, what tangible changes will you see in 6, 12, and 24 months? Be specific about metrics and program milestones.
• What commercial or supply commitments would you need from us to feel confident moving forward (lead-time guarantees, penalty clauses, errata handling process)? Options: Firm lead-time SLAs, Supply continuity clause, Escrow/last-time buy terms, Formal errata resolution SLA, Other
• Who needs to sign a mutual commitment to proceed (roles/titles), and what would be the minimum set of commitments you expect in that mutual plan?
• What would be the ideal timing and cadence for joint qualification gates and check-ins between our teams? Options: Weekly technical sync, Bi-weekly steering, Monthly executive review, Ad-hoc as needed
• What immediate next step would move this from conversation to action for you in the next 14 days? Options: Schedule joint test plan review, Provide evaluation boards, Sign NDAs and data exchange, Set up steering committee meeting, Other

Quick Snapshot — The Program in One Breath

• What is the program name, platform generation, and OEM you’re working against (short form)?
• How many months until your OEM platform freeze date? Options: <3 months, 3–6 months, 6–9 months, 9–12 months, 12–18 months, >18 months
• Who is the primary contact for network architecture decisions (role and team)?
• Which internal teams will be actively involved in device selection and qualification? Options: Vehicle Network Architecture, ECU Hardware Design, Software/AUTOSAR Integration, Central Electronics Platform, Supply Chain/Procurement, Quality/Validation, Other
• On a scale of urgency, how would you describe this decision? Options: Mission critical — cannot miss OEM freeze, High priority — tight window, Moderate — some flexibility, Exploratory — long-term

What Could Blindside Your Project?

• If a single unexpected issue appeared tomorrow (supply shortage, late errata, failing EMC), which one would be most likely to derail your freeze date? Options: Silicon errata discovered late, Supplier lead-time extension, EMC compliance failures, Sleep-power outliers, Interoperability with legacy ECUs, Other
• How often have you experienced late silicon errata or qualification blockers on recent programs, and how long did they typically delay you? Options: Never, Once, 2–3 times, More than 3 times
• Which of these supply/qualification risks keeps you up at night? Pick all that apply and briefly tell us why in the next question. Options: Single-source risk, Long lead times for automotive grade parts, In-flight silicon errata, Unexpected BOM changes, Vendor discontinuation/last-time-buy
• Tell us a concrete example of a past supply or qualification problem and what it cost you (time, rework, or lost launch).

Map the Reality — Your Current ECU & Network Layout

• How many separate ECU domains (logical groups or vehicle domains) are present today and how many ECUs per domain (approx)? Options: 1–3 domains, 4–6 domains, 7–10 domains, More than 10
• Which in-vehicle protocols are currently used across those domains? Options: CAN, CAN FD, LIN, FlexRay, 100BASE-T1/1000BASE-T1 Ethernet, Other
• Describe your legacy CAN topology: linear bus, star, multiple bridged sub-buses, or mixed — and where gateway points currently exist. Options: Linear bus, Star topology, Multiple bridged buses, Zonal sub-buses with gateways, Mixed — describe in next question
• Upload or paste (or summarize) the single-page logical topology or point us to the diagram — which nodes are the hardest to change?
• Which ECUs are considered ‘untouchable’ (cannot be redesigned in this program) and must be bridged or adapted? Options: Powertrain ECUs, Safety-critical ECUs (airbag/ABS), Telematics/Infotainment, Body control modules, ADAS sensors, None — greenfield

Where Performance Actually Breaks Down

• Which performance metric has been the toughest to meet in previous migrations: EMC, latency, or sleep-mode power? Options: EMC, Latency, Sleep-mode power, All three are tough, Other
• Share a recent test result or real-world symptom that shows the problem (e.g., specific EMC margin misses, latency spikes, or sleep current numbers).
• How often do these issues occur during validation—intermittent, reproducible under certain conditions, or continuous? Options: Intermittent, Reproducible under conditions, Continuous
• What has been the human or program impact when these performance gaps show up (delayed milestones, extra lab cycles, added BOM, customer escalations)?
• Which board-level or system-level levers have you tried (different transceivers, termination changes, shielding, software rate-limiting)? Please list what helped and what didn’t.

Who Needs to Feel Good About This Decision — And Why

• Thinking beyond the project lead—who are the five stakeholders that must sign off for production adoption? Options: Network Architect, ECU Hardware Lead, Systems Safety/A-IS, Platform Architect / Central Electronics, Supplier Quality, Purchasing/Commodity Manager, Other
• For each stakeholder type you selected, what does ‘good’ look like for them? (be specific — metrics, gates, or outcomes)
• Which acceptance metrics are non-negotiable for launch (pick up to three)? Options: EMC margins (dB) specified, One-way latency threshold (ms), Sleep-mode current (µA/mA), Protocol compliance (AUTOSAR/OPEN Alliance), Qualification gate pass-rate
• Who owns silicon qualification and who owns system integration — are these separate teams or a single owner? Options: Separate teams with handoff, Single owner for both, Cross-functional squad, Not yet defined
• How will you decide between a single-source integrated transceiver/switch solution versus mixed suppliers (trade-offs you care about)?

The Migration Tradeoffs You Haven’t Fully Named

• If keeping every legacy ECU unchanged meant a 12–18 month longer program, would you accept that delay, accelerate redesign, or look for bridging silicon? Options: Accept delay, Accelerate redesign, Choose bridging gateway silicon, Unsure — need options
• Which of these tradeoffs are you most willing to make to hit the freeze date? Options: Slightly higher BOM cost, Longer qualification testing before freeze, Temporary board-level workarounds, Constrained feature set at launch
• What performance compromises are absolutely off the table (e.g., cannot exceed X latency, cannot exceed Y sleep current)?
• How would you rank the following priorities for this program (1 highest to 4 lowest)? Options: Lowest latency, Lowest sleep power, Strongest EMC margin, Minimal BOM/qualification complexity
• Have you mapped a realistic migration path for ECUs that will remain CAN-based for several years? If so, how many phases and what are the phase criteria? Options: No plan yet, 1–2 phases, 3–4 phases, More than 4 phases

Supply & Qualification — The Unseen Timeline

• What are your typical lead-times for qualified automotive silicon today (NPI to qualified production) in months? Options: <6 months, 6–9 months, 9–12 months, 12–18 months, >18 months
• Do you require multiple independent silicon sources or is single-source acceptable with long-term supply guarantees? Options: Multiple sources required, Single-source acceptable with guarantees, Prefer multiple but possible single, Undecided
• Which qualification gates must be cleared before you can commit (select all that apply)? Options: AEC-Q100 electrical tests, EMC pre-compliance and system EMC, AUTOSAR protocol stack compliance, Functional safety reviews, Long-term reliability (HTOL), Silicon errata closure
• Who in your organization is the formal owner for supply continuity conversations and commercial commitments?
• If a vendor offered prioritized allocation or long-term product commitments, what contract or assurance terms would be required to make that meaningful to you?

Evaluation Readiness — Can We Recreate Your Roadblocks in the Lab?

• Do you already have evaluation boards and firmware that represent your topology, or will you need vendor-provided evaluation kits? Options: We have representative eval boards & FW, Need vendor evaluation kits, Hybrid — partial in-house setup
• Which of the following tests do you plan to run on evaluation hardware (pick all that apply)? Options: EMC pre-compliance, Latency and jitter under load, Sleep/wake current profiling, Protocol conformance (AUTOSAR/OPEN Alliance), Interoperability with legacy ECUs, Gateway throughput
• Do you have lab access and fixtures for EMC, long-duration sleep testing, and latency profiling, or would you need shared/vendor lab time? Options: Full in-house labs & fixtures, Need vendor/shared lab access, Need specific fixtures only, Unsure
• What data would convince you to adopt our silicon for the program (specific tests, thresholds, or reference scenarios)?
• Who on your team will run the hands-on evaluation and who will interpret the results for decisions?

Compliance & Interoperability — The Gates You Can’t Ignore

• Which standards compliance are mandatory for launch (AUTOSAR conformance, OPEN Alliance test profiles, IEEE PHY standards, ISO requirements)? Options: AUTOSAR conformance, OPEN Alliance compliance, IEEE 100BASE-T1/1000BASE-T1, ISO 11898 (CAN), Other
• Have you previously failed any compliance test (AUTOSAR, OPEN Alliance, or EMC) during qualification? If yes, what was the failure and how was it resolved?
• How important is backwards compatibility with existing CAN tooling and diagnostics for your long-term support model? Options: Critical — cannot change diagnostics, Important but adaptable, Low priority — can be redeveloped
• When bridging CAN to Ethernet, which interoperability scenarios concern you most (message translation latency, diagnostic transparency, security, clocking)? Options: Message translation latency, Diagnostic transparency, Security implications, Time synchronization/clocking, Other
• If we provided a reference gateway design that preserved diagnostic interfaces and reduced BOM count, how would that change your decision calculus? Options: Significantly, Somewhat, Little, No change

Decision Rhythm — Milestones, Owners, and The Real Deadline

• Working backwards from your OEM freeze, what intermediate decision milestones do you need (e.g., eval board signoff, EMC signoff, sample order, supplier contract)?
• Who will be the final approver at freeze (role/title) and what evidence will they require to sign off?
• How flexible is your freeze date if a credible mitigation plan (e.g., phased acceptance, conditional supply commitment) is proposed? Options: Not flexible, Flexible by a few weeks, Flexible by a few months, Depends on mitigation details
• What internal escalations or review forums must be included for any supplier selection (steering committee, platform board, procurement review)? Options: Steering committee, Platform architecture board, Procurement review, Safety/regulatory board, Other
• If we propose a joint, time-boxed qualification plan, who should be invited to the kick-off and who will drive weekly execution?

A 90-Day Sprint — What Would Make This Feel Like Progress?

• If we agreed on three concrete deliverables for the next 90 days, what would you want them to be (e.g., evaluation boards in your lab, initial EMC pretest report, supply term sheet)?
• Which of these would make you more confident in a vendor: prioritized silicon allocation, early engineering samples, or collaborative lab time? Options: Prioritized allocation, Early engineering samples, Collaborative lab time, All of the above
• What decision criteria would you use at the end of the 90 days to either continue with a single vendor or open to additional suppliers?
• Who should we schedule as the 90-day sponsor from your side (name/role) and how often should we meet to track progress? Options: Weekly, Bi-weekly, Monthly, Ad-hoc
• What would count as a red flag at 90 days that requires pausing the plan or escalating immediately? Options: Failed EMC pretest, Major interoperability bug, Supplier lead-time slip >X weeks, Unresolved errata with functional impact

Quick Pulse: Where Are We Right Now?

• How close are you to starting silicon qualification for this vehicle program? Options: Not started (requirements only), Planning phase (test plans defined), Initial lab tests under way, Evaluation complete — ready to begin qualification, Already in qualification
• Who is the single accountable owner for qualification readiness on your side (name/role/team)?
• Which evaluation hardware and firmware do you already have available? Options: Reference evaluation board(s), Customer custom carrier boards, Early silicon samples only, Working firmware/drivers, No hardware yet
• What is your OEM platform freeze date (or target design lock)? Options: < 3 months, 3–6 months, 6–9 months, 9–12 months, > 12 months, Not defined
• How confident do you feel in the evaluation results so far (EMC, latency, sleep power)? Options: Very confident, Somewhat confident, Mixed signals — needs clarity, Not confident at all
• What supply or qualification lead-time constraints are already impacting your schedule? Options: Long-lead silicon samples, Test fixture procurement, Lab booking windows, No constraints yet, Other

If We Slip a Month, What Breaks First?

• What’s the real cost to your program if silicon qualification is delayed by one production month? Options: Minor schedule risk, Rework on late ECUs, Miss OEM platform freeze — high cost, Program pause or deferral, Don't know / need analysis
• Which component or activity has the longest lead time that could cause that one-month slip? Options: Silicon samples, Antenna or harness procurement, EMC chamber bookings, Firmware development, Supplier approvals
• Who on your side is empowered to re-prioritize work to avoid that slip, and have they done so before?
• How does the rest of your organization (platform architects, OEM integrators, program managers) feel about the current schedule pressure? Options: Very concerned / high escalation, Wary but manageable, Calm — confident in mitigation, Unaware / not aligned
• What would reduce that schedule risk most effectively (e.g., additional test capacity, faster silicon, alternate supply)? Options: Extra test capacity, Parallel qualification paths, Expedited silicon samples, Alternate supplier or part, Clearer acceptance gates

Are Our Labs Really Ready — or Just Ticking Boxes?

• If you tried a full qualification run next week, what in your lab setup would be most likely to fail first?
• Which of the following lab capabilities are already in-house and validated for this program? Options: AEC-Q environmental chambers, EMC chamber with automotive setups, Precision latency measurement rigs, Low-power sleep-mode measurement fixtures, Automated regression test benches
• Do you have the required test fixtures, harnesses, and measurement harness drawings that match your production ECU boards? Options: All fixtures ready and validated, Fixtures ready but need validation, Fixtures need fabrication, No fixtures yet
• Who controls lab access and booking priorities (name/role), and is remote access available for our engineers? Options: Program lab manager, Plant/operations, Third‑party test house, No single controller / ad hoc
• Which external test houses or OEM labs will you rely on, and have they certified our measurement methods before?
• Are there any upcoming blackout dates for lab time (OEM audits, certification windows) that could block qualification? Options: Yes — known dates, Possibly — tentative bookings, No blackout dates, Unsure

Do the Data Tell a Clear Story — or a Riddle?

• Which single test result would cause you to stop and redesign the board rather than continue qualification?
• Please share the current numerical results or ranges you have for EMC, latency, and sleep-mode power (or attach links to reports).
• Have you defined clear pass/fail gates for each critical metric (EMC margins, latency headroom, sleep current thresholds)? Options: Yes — fully defined, Partially defined, Not yet defined, OEM defines gates only
• Are evaluation boards producing consistent, repeatable results across runs and sites? Options: Consistent across runs/sites, Some variability — tolerable, High variability — concerning, Not tested across sites
• Who independently reviews and signs off the raw data (test engineer, system architect, OEM verifier)? Options: Internal test engineer, System/network architect, OEM verifier, Third‑party lab
• Have any silicon errata emerged from evaluation that require board-level workarounds or firmware patches? Options: Yes — documented errata, Minor issues resolved, No errata seen, Unknown / under investigation

Who’s Holding the Integration End — and How Pulled Are They?

• If integration surfaces a protocol or timing incompatibility, what is your escalation path and expected time-to-resolution?
• Which software stacks and middleware have you committed to for this project (AUTOSAR release, OPEN Alliance profiles, proprietary gateways)? Options: AUTOSAR Classic — version specified, AUTOSAR Adaptive, OPEN Alliance BroadR-Reach / TSN profiles, Proprietary stacks, Not yet decided
• Are firmware drivers and BSPs for our silicon already integrated into your build and regression pipelines? Options: Fully integrated, Partially integrated, Planned but not done, Not started
• Who are the owners for software integration, test automation, and gateway mapping (names/roles)?
• Do you anticipate needing engineering support from us for firmware bring-up, driver fixes, or lab debugging during the first 90 days? Options: High support needed, Moderate support, Minimal support, No support
• If a protocol compliance gap is discovered, what trade-offs are you willing to consider (extra hardware, firmware workaround, relaxed spec)? Options: Hardware workaround, Firmware patch, Redesign ECU, Relax spec with OEM approval, Other

How Will We Catch Fires Before They Burn the Schedule?

• Which single risk do you believe has the clearest plan to fail safely (i.e., has no mitigation)?
• Do you maintain a formal risk register for qualification with named mitigations and owners? Options: Yes — actively maintained, Yes — but needs updating, No formal register, We track risks informally
• Which mitigation levers are most available to you today (choose all that apply)? Options: Extra test slots, Alternate silicon/batches, Board-level workarounds, Firmware fallbacks, Supplier escalation channels
• Do you have a fallback silicon or secondary supplier path if the primary part misses milestones? Options: Yes — qualified alternate, Candidate alternate under evaluation, No alternate available, Not applicable
• How quickly can your team implement a board-level workaround if an errata demands it (days, weeks)? Options: < 1 week, 1–3 weeks, 3–6 weeks, > 6 weeks, Unknown
• What level of commercial or supply commitment from us would materially reduce your program risk (e.g., allocation, buffer stock, long‑term supply agreement)?

If We Could Agree Right Now, What Would You Ask For?

• What are the three non-negotiable deliverables you need from us before you’ll greenlight a qualification kickoff?
• Which milestones would you expect in the first 90 days after kickoff? Options: Test fixture validation, First full EMC run, Latency benchmarking complete, Sleep-power verification, Integration sprint 1 complete
• What documentation and artifacts must be in place for you to trust our parts (e.g., datasheets, AEC-Q reports, known errata list, test-method descriptions)? Options: Full datasheet set, AEC-Q100 reports, Known errata and workarounds, Test method & setup descriptions, Reference firmware
• What cadence and format of status updates do you want from us (weekly written, weekly call, dashboard access)? Options: Weekly written summary, Weekly sync call, Daily stand-ups during runs, Shared dashboard with live results, Ad hoc as needed
• Are there any contractual, procurement, or compliance blockers we should resolve before qualification begins? Options: Commercial terms, Supply commitments, NDA / IP terms, Regulatory/compliance paperwork, None
• What would make you feel emotionally confident that this program will hit the OEM freeze date?

Quick Orientation: Your Program in One Line

• What is the program name, OEM platform, and target platform-freeze (OEM freeze) date?
• Who is the primary decision owner for network architecture and who signs the final silicon qualification? Options: Network Architect (Tier‑1), ECU Hardware Lead (Tier‑1), OEM Central Electronics, Program Manager, Procurement/Commodity, Other
• Which vehicle domains and legacy buses must be supported on this program? Options: Powertrain (CAN/CAN FD), Body (CAN/CAN FD), ADAS/Sensors (Ethernet/CAN), Infotainment (Ethernet), Lighting/Comfort (LIN), Safety/Critical (FlexRay/CAN)
• What is the hard production start or silicon qualification deadline you’re working toward? Options: < 6 months, 6–9 months, 9–12 months, 12–18 months, > 18 months
• Which single metric will make leadership say 'we made the right choice' for this network design? Options: EMC margin, Latency headroom, Sleep-mode power, Protocol interoperability, Supply continuity, Total BOM/Cost

If You Could Snap Your Fingers, What Would This Architecture Fix?

• If you could wave a wand and eliminate one persistent network problem on this program, what would it be?
• Which current limitation of transceivers, switches, or gateways causes the most schedule anxiety for your team?
• Which of these outcomes feels most urgent to avoid: missed OEM freeze, failed EMC, missed latency spec, or unacceptable sleep power? Options: Missed OEM freeze, Failed EMC testing, Missed latency spec, Unacceptable sleep power, Other
• How does this problem show up politically across stakeholders—who is most vocal, and who quietly tolerates the risk?
• Tell us about a past decision on a similar program that looked good on paper but caused problems later—what happened?

Where Risk Hides in Plain Sight

• Which single qualification or supply risk do you believe people are underestimating for this program?
• Which long‑lead or single‑sourced components are on your risk register today? Options: PHY silicon, Switch silicon, Gateway SoC, Magnetics/Connectors, Special packaging, Other
• Have you previously accepted silicon errata with board‑level workarounds? Tell us the most impactful example and how it felt to manage.
• How mature are your contingency plans if a device fails qualification—do you have parallel suppliers, redesign budgets, or timeline buffers? Options: Parallel suppliers in place, Budgeted redesign contingency, Timeline buffer only, No practical contingency
• On a scale from 1–5, how comfortable are you with accepting board‑level workarounds to meet schedule (1 = never, 5 = regularly)? Options: 1, 2, 3, 4, 5

Mapping Your Current Reality — Show Me the Network

• If I opened your architecture diagram today, what single thing would surprise me about how legacy and Ethernet domains are bridged?
• Please describe the ECU domains, gateway points, and any existing zonal switch locations we must integrate with.
• Which ECUs are fixed (cannot be changed before production), and which are candidates for redesign or replacement? Options: Fixed (production locked), Low-risk redesign candidate, Major redesign candidate, Unknown / TBD
• What are typical bus lengths, topology (daisy, star, multi-drop), and termination practices for your CAN domains?
• How many gateway translation points do you expect between CAN domains and the zonal Ethernet backbone? Options: 0–1, 2–4, 5–8, 9+

What Does 'Good' Actually Look Like for Everyone?

• Which stakeholder groups have the most divergent definitions of success for this program? Options: OEM Central Electronics, Vehicle Network Architect, Tier‑1 ECU Hardware, Systems Integration, Procurement/Commodity, Other
• For each stakeholder, what are the measurable acceptance criteria we must meet (EMC margins, latency numbers, sleep current targets, protocol compliance)?
• What are the non‑negotiable protocol compliance requirements (AUTOSAR stack versions, OPEN Alliance PHY profiles, CAN FD timing, etc.)? Options: AUTOSAR version, OPEN Alliance compliance level, CAN/CAN FD timing classes, Ethernet TSN requirements, Other
• How will success be signed off—functional signoff, lab report thresholds, supplier qualification board sign‑off, or OEM final acceptance? Options: Lab test reports, Functional signoff by architect, Supplier qualification board, OEM final acceptance, Other
• Which timeline constraints (OEM freeze, market launch) feel most at risk today and why?

Can We Honestly Deliver That on Your Board?

• What kinds of board‑level workarounds would you accept to preserve program timing, and which would you categorically reject?
• Do you require that any silicon errata be resolved in silicon before production, or will you accept documented mitigations? Options: Resolve in silicon before production, Documented mitigations acceptable, Case-by-case discussion, Unsure
• How much PCB redesign schedule and budget is realistically available for workaround integration? Options: None, < 2 weeks / minimal budget, 2–6 weeks / moderate budget, > 6 weeks / significant budget
• Are there thermal, mechanical, or EMC constraints on board layout that we must accommodate (e.g., restricted stacking, CAN stub limits)?
• Who owns board-level fixes during qualification—your engineering team, the Tier‑1, or a co-engineering model? Options: Customer (Tier‑1/OEM), Vendor co-engineering, Shared ownership, Other

Testing, Labs, and the Evidence That Closes Deals

• If we could deliver one lab result tomorrow that would remove doubt, which single test would you want to see (EMC margin, sleep current, latency under load, AUTOSAR interoperability)? Options: EMC margin, Sleep-mode current, Latency under load, AUTOSAR/OPEN Alliance interoperability, Other
• Which tests must run in your lab versus tests you’ll accept from vendor or third‑party labs? Options: Customer lab only, Vendor lab accepted, Third-party accredited lab, Combination
• What are your pass/fail thresholds for EMC, latency (max jitter/RTT), and sleep-mode power (µA or mW)? Please be specific.
• Do you require AUTOSAR conformance reports or OPEN Alliance PHY compliance certificates as part of qualification? Options: Both AUTOSAR and OPEN Alliance, Only AUTOSAR, Only OPEN Alliance, Neither, Unsure
• What level of access can we expect to your lab, fixtures, or testbeds during evaluation (remote access, on-site support, data sharing)? Options: Full on-site access, Scheduled lab time, Remote data access only, No access / vendor-only

Commitments That Keep Programs Alive

• Which supplier commitment would change everything for you—firm lifetime supply, documented errata policy, price stability, or something else? Options: Lifetime supply guarantees, Formal errata/mitigation policy, Price stability/long-term pricing, Roadmap visibility, Other
• What supply continuity mechanisms do you expect (dual sourcing, long lead buys, managed safety stock)? Options: Dual sourcing, Lifetime buys, Safety stock managed by supplier, Just-in-time procurement, Other
• How should we handle silicon errata notifications and mitigations—advance notice, shared mitigation plans, compensation, or replacement?
• What commercial acceptance gates are mandatory before you move to production (NRE, qualification signoff, PPAP, other)? Options: NRE complete, Qualification signoff, PPAP/Production Approval, Supply agreement signed, Other
• What escalation path or program governance structure do you require for unresolved technical issues? Options: Weekly tech working group, Direct exec escalation, Dedicated program manager, Supplier-STG alignment, Other

Next Steps — What Would Make This Conversation Useful?

• If we stopped after this discovery, what would you regret not having captured or agreed upon?
• Which follow‑up deliverables would be most valuable: evaluation kit, tailored test plan, joint lab run, or detailed commercial term draft? Options: Evaluation kit with firmware, Tailored EMC/latency test plan, Joint lab qualification run, Commercial term draft, Other
• Who needs to attend the next technical deep‑dive to make decisions (names and roles)?
• What is your preferred timeline to receive an evaluation board and initial test data? Options: Immediate (1–2 weeks), 2–4 weeks, 1–2 months, 2+ months, Not sure
• How would you prefer us to track progress and share artifacts—a shared workspace (preferred), weekly call, or formal milestones in a project plan? Options: Shared workspace (e.g., Confluence/Share), Weekly sync calls, Formal project milestones, Ad hoc emails
• Anything else—technical, political, or emotional—that we didn’t ask but should know to help you succeed?