Quick check — Who’s actually in the room?

• Which people or roles will be directly involved in deciding whether to adopt a new signoff solution for this node? Options: Director of Physical Design, VP of Engineering, CFO/Finance, Signoff/PD Engineers, CAD/Tooling Lead, Foundry Point-of-Contact, Program Manager, Other (please name)
• Who is the single person we should view as the primary decision owner for this initiative? Options: Director of Physical Design, VP of Engineering, CFO/Finance, CAD/Tooling Lead, Program Manager, Other (name)
• Who holds the budget approval authority for signoff tool purchases and pilot compute commitments? Options: CFO/Finance, VP of Engineering, Director of PD, Procurement, Distributed across teams, Other (please specify)
• How do your stakeholders prefer technical validation to be presented (e.g., numeric correlation, foundry letter, side-by-side silicon comparison, runtime benchmarks)? Options: Numeric correlation to silicon, Foundry certification/letter, Side-by-side silicon plots, Runtime and capacity benchmarks, Cost/risk reduction model, Combination of the above, Other
• Tell us about a recent technical recommendation that won approval — what helped that become a yes?

If a false-pass happened: the real consequences

• If a false-pass escaped to fab on this tapeout, what would the practical impact be (choose all that apply, then quantify below)? Options: Mask/NRE cost impact, Schedule slip (months), Customer/partner damage, Increased engineering overtime, Revenue impact, Other (please specify)
• Give specific numbers or ranges for the biggest impacts you selected above (e.g., $ mask cost, months of delay).
• How do those potential outcomes feel to the leadership team—panic, urgent, manageable, or tolerable risk? Options: Panic/critical, Highly urgent, Manageable with remediation, Tolerable risk
• When a risky signoff decision comes up, how is it typically escalated (who’s called, how fast, and what evidence do they require)?
• Have you calculated an internal threshold for acceptable respin probability or expected cost that would justify a tool change? If so, what is it? Options: Yes — we have a numeric threshold, We have a qualitative threshold, No formal threshold

Where 'good enough' becomes unacceptable — defining ‘good’ for each stakeholder

• When you hear claims like '1% correlation to silicon', which stakeholder benefit does that signal first to you—cost avoidance, schedule confidence, engineering velocity, or something else? Options: Cost avoidance (fewer respins), Schedule confidence (hit tapeout), Engineering velocity (fewer debug cycles), Foundry acceptance/certification, Other
• For each role below, please select the top 1–2 success metrics that would convince them a pilot worked (we’ll ask you to map values next): Director of PD, VP Engineering, CFO, Signoff Engineers. Options: Timing correlation to silicon (%), Runtime on largest design (hours), Foundry certification letter, Reduction in respin probability (%), Fewer signoff closures (ECOs) post-silicon, Lower total engineering hours
• Please assign numeric targets (or qualitative thresholds) for the most important success metrics you just selected — list role then target (e.g., Director of PD: correlation ≤1.0%).
• Which stakeholder will prioritize runtime and capacity concerns over correlation accuracy, and which will prioritize correlation over runtime? Options: Director of PD (accuracy), VP Engineering (balanced), CFO (cost/runtime), Signoff Engineers (runtime), Varies by person — explain below
• How will each stakeholder know the pilot is successful on day one, week four, and at pilot close? Describe the tangible signals for each milestone.

Hard dates, tapeout windows, and absolute constraints

• What are the non-negotiable tapeout deadlines, foundry submission freezes, or blackout periods that define our latest possible pilot completion date? Options: Mask submission date (provide date), Foundry freeze windows, Customer delivery deadline, No strict freezes — flexible timeline, Other (please detail)
• Please provide the target tapeout date, mask commit date, and any hard cutover windows (dates).
• How much schedule slack do you typically have between signoff completion and tapeout, in weeks? Options: >12 weeks, 8–12 weeks, 4–8 weeks, <4 weeks
• If a pilot delivers later than expected, what are the immediate operational consequences for the program (e.g., miss tapeout, accelerate other tasks, accept risk)? Options: Miss tapeout (critical), Accelerate other tasks (cost increase), Accept higher respin risk, Re-plan next tapeout phase, Other
• Are there internal approval gates or board-level reviews tied to this node transition that we should align to? If yes, name them and their timing.

Who owns the data, access, and IP — and what must be protected?

• What type of access can you provide for a pilot run on your tapeout-ready design: full design DB, extracted netlist, masked/redacted data, or only summarized outputs? Options: Full design DB (on-prem), Full design DB (secure cloud), Extracted netlist only, Masked/redacted design data, Summarized/exported outputs only, Other (specify)
• Are there IP, export control, or foundry NDAs that restrict where or how we can run the pilot (on-prem only, approved cloud, partner facility)? Options: On-premise only, Approved cloud providers only, Partner/Foundry lab only, No restriction beyond NDA, Other (please detail)
• What compute infrastructure do you have available for signoff on the largest designs (select all that apply and indicate rough capacity below)? Options: Local cluster (X nodes), Private cloud (capacity), Public cloud (AWS/GCP/Azure), HPC partner, No dedicated capacity — will need provisioning
• How sensitive is your team to handing source-level design data to an external vendor for benchmarking? Describe feelings and any required mitigations.
• What license or foundry documentation constraints must we satisfy before running correlation work (e.g., SPICE deck, PDK access, foundry NDA)?

Stories that matter — past correlation gaps and what you learned

• Think about your last node transition where correlation drifted—what exactly diverged (timing, power, IR, corners) and by how much?
• How did you discover the divergence—silicon measurements, post-silicon debug, customer complaints, or gate-level failures? Options: Silicon measurements, Post-silicon debug, Customer field issues, Foundry feedback, Internal QA failures, Other
• What root causes were suspected or confirmed (extraction differences, OCV/SSO modeling, aging, PVT corners, data translation)? Options: Extraction differences, On-chip variation (OCV/SSO), Aging/modeling gaps, Corner definitions mismatch, Data translation/format errors, Other
• How long did triage and remediation take, and what was left unresolved at tapeout? Options: <1 month, 1–3 months, 3–6 months, >6 months, Ongoing/unresolved
• What investigative artifacts exist from that effort (scripts, correlation reports, silicon-vs-tool plots) that we could review to accelerate root-cause analysis? Options: Correlation plots, Correlation scripts, Post-silicon logs, None readily available, Other (list)

Picking tradeoffs — accuracy vs runtime vs cost

• If improving correlation required more runtime or compute cost, how would your team prioritize accuracy vs schedule vs budget? Options: Accuracy first (accept cost/time), Balance accuracy and runtime, Minimize runtime/cost (accept modest accuracy loss), Depends on design — specify
• What is the CFO’s maximum tolerable spend increase (percentage or $) in order to materially reduce respin risk for this node? Options: No increase allowed, <10% increase, 10–25% increase, >25% increase, Not sure / needs discussion
• Which of these tradeoffs would be a deal-breaker for implementation after a successful pilot? Options: Significant runtime regression, Unresolved correlation gaps >X%, Lack of foundry certification, Major workflow disruption for engineers, Unacceptable IP handling
• How tolerant is your engineering team of changing debugging/reporting formats if it materially improves correlation? Options: Very tolerant — accuracy wins, Some friction but acceptable, Prefer minimal change, Not tolerant
• Who on your team would we involve to evaluate the runtime/cost tradeoff practically (names and roles)?

A pilot they'd actually green-light — scope, signals, and governance

• What minimal pilot scope would the Director of PD and VP Engineering sign off on tomorrow (single block, multi-block subset, full-chip run)? Options: Single design block, Multi-block subset, Full-chip (production) design, Golden tapeout comparison only, Other (describe)
• List the top 3 success signals that would convince each stakeholder to move from pilot to phased rollout (e.g., correlation ≤1% on critical corner, runtime <X hours on largest job).
• What governance model will you require to resolve any correlation gaps discovered during pilot (weekly tech reviews, escalation to VP, joint debug war room)? Options: Weekly technical review, Daily war-room until closed, Escalation to VP/Director, Joint engineering debug sessions, Other (specify)
• How much compute and engineer time can you commit to the pilot (e.g., number of cores, nodes, and FTE hours per week)?
• Who will sign final pilot acceptance and what evidence do they need attached to the acceptance (reports, foundry letter, runtime logs)? Options: Director of PD, VP of Engineering, CFO (for budget signoff), Program Manager, Other (name)

Immediate next steps — what we need from you to start

• Which of the following can you supply within two weeks to get a pilot scheduled (select all you can provide quickly)? Options: Tapeout-ready design DB, Extracted netlist, Foundry PDK + cert notes, Access to on-prem cluster, License entitlements, Executive sponsor introduction
• Who is the day-to-day technical contact we should schedule initial workshops with? Please provide name, role, and preferred contact method.
• What are your preferred governance cadences for the pilot (weekly sync, biweekly executive check-in, ad-hoc escalation)? Options: Weekly technical sync, Biweekly exec check-in, Monthly review only, Ad-hoc as issues arise, Other (specify)
• Is there anything else we should know now that would dramatically speed up or block a pilot (security scans, procurement lead times, travel restrictions)?
• Finally — on a scale from 1–10, how ready is your team to start a technical pilot to validate signoff correlation on this node (1 = not at all, 10 = ready now)? Options: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10

Start Here: Map Your Signoff Landscape

• Which signoff disciplines are part of your current final-quality flow for the latest tapeout? Options: Static Timing Analysis (STA), Signoff Power/IR, EM/Current Density, Physical Verification (DRC/LVS), Reliability/Aging, Other
• Which primary signoff tools and versions did you run for that tapeout (list vendor and tool name, e.g., Synopsys PrimeTime vX.Y)?
• What process node and tapeout date are we discussing? Options: 7 nm, 5 nm, 3 nm, N5/N3 derivative, Other (please specify)
• Roughly how large was the design you used for signoff (logic cells / mm^2 / flip-flops / hierarchical blocks)?
• Do you maintain a single extracted netlist that feeds timing, power and IR signoff—or do you stitch results from separate point tools? Options: Single unified extracted netlist, Separate point tools with translation, Hybrid (some shared, some translated), Not sure / need to check

Are You Comfortable Betting the Tapeout on Your Current Flow?

• How confident are you that your current signoff flow would catch a silicon-critical timing or power issue before tapeout? Options: Extremely confident, Somewhat confident, Neutral / Unsure, Not confident
• What margin of timing/power correlation vs actual silicon do you consider acceptable for this node? Options: ≤1%, 1–2%, 2–3%, >3%
• When you say 'confident' or 'not confident,' what specific evidence or lack of evidence drives that feeling?
• If your current flow missed a critical violation, what would be the immediate business impact you expect (choose all that apply)? Options: Respin and mask cost, Schedule slip (months), Revenue loss for product cycle, Customer escalations, Other
• Who in your organization would need to sign off to accept the current level of risk on this tapeout? Options: Director of Physical Design, VP Engineering, CFO, Foundry POC, QA/Validation Lead, Other

Where Have Results Surprised You — The Moments That Changed Trust

• Tell us about the most recent time your signoff results diverged from silicon—what happened, and why did it matter?
• How often do you see post-silicon delta between signoff predictions and measurements that exceed your acceptable margin? Options: Never, Occasionally (1–2 designs/year), Regularly (every tapeout), Frequently (multiple blocks per tapeout)
• Which corners or modes tend to show the largest correlation gaps (e.g., SS slow, FF fast, FF slow + TT aging)? Options: Slow corners (SS/TT slow), Fast corners (FF), Aging/BTI corners, Voltage droop/IR corners, PVT extremes, Other
• Do you have concrete artifacts (timing reports, margin plots, silicon scan data) from those surprises you can share for analysis? Options: Yes — full reports available, Yes — partial redacted data, No — not available, NDA required to share
• How did those surprises change internal trust in the toolchain or people responsible for signoff?

Who's Actually Signing Off — Roles, Process, and Politics

• Who has final signoff authority today—and do you ever have conflicts between owners that delay decisions?
• Which formal staging gates does a design pass through before physical tapeout (e.g., block-level signoff, chip-level signoff, foundry pre-check)? Options: Block-level signoff, Chip-level signoff, Integration signoff, Foundry pre-check, No formal gates
• Is your signoff flow and approval path documented and version-controlled? Options: Fully documented and versioned, Partially documented, Informal/tribal knowledge, Not documented
• What escalation path do you follow when a signoff disagreement arises (who resolves disputes and how long does it take)?
• How would you describe stakeholder sentiment toward switching or augmenting the signoff toolset right now? Options: Supportive, Cautious but open, Resistant, Divided

What's Breaking the Build: Translations, Scripts, and Tool Handoffs

• To what extent do handoffs and file translations between tools introduce uncertainty in your results? Options: Major source of uncertainty, Somewhat problematic, Occasional issues, Rarely an issue
• Which extraction and signoff components do you run in-house vs. via third-party tools (extraction, liberty/timing models, parasitic extraction, SDF/FSDB generation)? Options: In-house, Vendor tool, Hybrid, Not applicable
• Do you rely on manual scripts to translate between formats (for example, GDS->LEF, SPEF->SPEF-PAR)? How stable are those scripts? Options: Yes, many scripts and fragile, Yes, but well-maintained, No, minimal scripting, Not sure
• Have you traced any false-positives or false-negatives back to a translation or netlist mismatch? Please describe one example.
• Would consolidating to a single shared extracted netlist be feasible for you in a pilot? Options: Yes — ready now, Possible with some engineering effort, Difficult — organizational constraints, Not feasible

How Close Is Your Compute to Breaking?

• When you run full-chip signoff on the largest designs, how often do you hit queue or memory bottlenecks that delay delivery? Options: Always, Often, Sometimes, Rarely, Never
• Describe your compute environment for signoff: on-prem cluster, cloud burst, hybrid, or workstation-based? Options: On-prem HPC cluster, Cloud (public), Cloud (private), Hybrid on-prem + cloud, Workstations only
• What are typical runtimes for full-chip STA and power jobs on your largest design (give ranges in hours/days)?
• What peak node/core/memory configuration do you have available for signoff jobs today? Options: ≤64 cores, 65–256 cores, 257–1024 cores, >1024 cores, Unsure / contact infra
• If a new engine required 2–4× more memory per job to meet correlation goals, how feasible is that scale-up for you? Options: Easily feasible, Feasible with budget request, Hard — long lead time, Not feasible

How Do You Detect and Handle False Passes?

• When a design ships and later shows a field failure or silicon mismatch, how do you determine whether signoff issued a false pass?
• What methods do you use to validate signoff predictions prior to tapeout (internal silicon correlation labs, golden masks, targeted silicon brings)? Options: Post-silicon measurement, Hardware-in-the-loop, Golden corner correlation, Regression against previous tapeouts, None
• How long does it typically take from detecting a mismatch to completing root-cause analysis and assigning corrective actions? Options: <1 week, 1–4 weeks, 1–3 months, >3 months
• Do you track false-pass incidents in a central defect/capture system and trending dashboard? Options: Yes, with dashboards, Yes, but manual tracking, No formal tracking, Not sure
• How tolerant is leadership to a small, quantified residual risk of false pass in exchange for faster runtimes or lower compute cost? Options: Very tolerant, Somewhat tolerant, Not tolerant, Depends on magnitude

If You Could Improve One Thing Before Tapeout, What Would It Be?

• If you had to pick the single most valuable improvement we could deliver before your next tapeout, what would it be (accuracy, runtime, capacity, foundry certification, debugging)? Options: Accuracy/correlation, Reduced runtime, Compute capacity and scalability, Foundry certification, Better debugging/reports, Other
• What numeric targets would make you comfortable to move forward—correlation % target, runtime threshold, and compute profile?
• Who would be the executive-level sponsor we should align to that outcome (name/title)?
• What would be an acceptable pilot scope and duration to prove that improvement (single block, full-chip; weeks/months)? Options: Single block (2–4 weeks), Multi-block (1–3 months), Full-chip (2–6 months), Other
• What would a visible sign that this single improvement “worked” look like for your team and leadership?

Evidence Locker — What Can You Share Right Now?

• Which of the following artifacts can you provide for an initial benchmark engagement? Options: Tapeout-ready netlist, SDC/timing constraints, Parasitic extraction files (SPEF/ASP/other), Foundry PDK & signoff decks, Post-silicon measurement data, None
• Are there legal or IP constraints (NDA, limited sharing) we need to know before you can provide those artifacts? Options: NDA in place — ready to share, NDA needed, Can share redacted data, Restrictions prevent sharing
• How quickly could you make these artifacts available to an external partner (immediately, weeks, months)? Options: Immediately, Within 1–2 weeks, Within 1–4 weeks, More than a month
• Are there specific security controls or review processes required before we access your files (air-gapped transfer, VPN, onsite-only)? Options: Air-gapped transfer, VPN+SFTP, Onsite-only review, Standard NDA access, Other
• Who is the technical contact that owns the artifacts and will coordinate transfer (name/title/email)?

Final Reflection: What Keeps You Up at Night About This Tapeout?

• If you imagine the worst-case scenario on this tapeout, what is the chain of events you fear most?
• What past experience, story, or decision still affects how you approach signoff today?
• If you could hand us one piece of context that would dramatically speed troubleshooting, what would it be?
• Realistically, how quickly are you prepared to run a technical benchmark if we demonstrate a secure, low-friction data path? Options: Immediately, Within 2 weeks, 1–2 months, Longer / need planning
• Who should we loop in next from your team to accelerate discovery and set up a pilot (name/title)?

Getting Comfortable Together

• Tell us your role and the primary tapeout or project this pilot would support. Options: Director, Physical Design, VP, Engineering, Signoff Engineer, Program Manager, Other
• What is the target tapeout date or milestone we should design the pilot around? Options: Within 1 month, 1–3 months, 3–6 months, 6+ months, No firm date
• Who will be our day-to-day technical contact and who will be the executive sponsor for decisions?
• Which process node and foundry node is this pilot targeting (e.g., 7nm, 5nm, 3nm)? Options: 7nm, 5nm, 3nm or below, Other / custom node, Undecided
• Give one sentence that best captures your biggest worry about this upcoming tapeout.

If This Goes Sideways, Who Feels It Most?

• How confident are you that your current signoff flow would catch a critical silicon-timing divergence at this node? Options: Very confident, Somewhat confident, Unsure, Not confident
• If a false-pass occurred on this tapeout, what would the primary consequence be for your team or company? Options: Mask respin + months schedule slip, Significant revenue hit, Reputation damage with customers/foundry, Resource reallocation, Other
• Historically, how many tapeouts in your org have required a respin or significant patch due to signoff misses in the last 3 years? Options: 0, 1, 2–3, 4+, Unsure
• Who inside the company would be most pressured or exposed if the pilot revealed a mismatch between tools and silicon? Options: Director, Physical Design, VP, Engineering, CFO/Finance, CTO, Program Manager, Other
• How does the prospect of a respin make you or your team feel—frustrated, anxious, resigned, or something else? Options: Frustrated, Anxious, Under pressure, Motivated to change, Other

Are You Confident Your Data Can Tell the Whole Story?

• Do you have accessible silicon measurement data from prior tapeouts for correlation (e.g., silicon timing, power, on-chip variation measurements)? Options: Full dataset available, Partial dataset available, Only summary metrics, No silicon data available, Restricted/under NDA
• Which foundry and PDK artifacts can you provide for the pilot without additional approvals (select all that apply)? Options: RC corners / extracted decks, SPICE models, Variability/OPC reports, Foundry characterization guides, Nothing currently available
• Are there IP or NDA constraints that would limit sharing files with our engineering team or require onsite-only execution? Options: No constraints, Standard NDA required, Onsite or air-gapped only, Cannot share IP at all, Unsure—need to check
• What formats and sizes are your design data and signoff inputs (e.g., full-GDSII, block-level LEF/DEF, extracted SPEF), and are they ready for transfer? Options: Full-chip GDSII, Block LEF/DEF + RTL, Extracted SPEF/CSPEF, Compressed archives >1TB, Not packaged yet
• If any critical data is missing today, how long would it take to assemble and approve it for pilot use? Options: <1 week, 1–2 weeks, 2–4 weeks, 1–2 months, Longer / unknown

What Would Break the Pilot Before It Starts?

• If we had to begin the pilot next week, what single technical or organizational barrier is most likely to stop us?
• Do you have the necessary tool licenses and entitlement for the test scope we discussed (timing, power, extraction, reliability)? Options: All licenses available, Partial licenses—need temporary keys, No licenses—require our tools, Unsure
• Who controls the licensing and sandbox environments (internal tools team, vendor, cloud provider), and how quickly can they grant access? Options: Internal licensing team, Vendor-managed, Cloud provider, Combination, Unsure
• Have you faced runtime or capacity surprises on your largest designs before? If yes, please describe one incident and the impact.
• What security or IP governance checks must be completed before we can move files between teams or to the cloud? Options: Signed NDA, Data handling SOP, Onsite-only execution, Encrypted transfer + audit, None required / already cleared

What Would It Take to Run Your Biggest Design Smoothly?

• Describe the largest design or block (size, cell count, corners/MCMs) you expect the pilot to analyze.
• What are your acceptable runtime expectations for the largest full-chip or block runs (wall-clock and walltime per corner)? Options: <24 hours, 24–72 hours, 72–168 hours, >1 week, Unsure
• What compute infrastructure will be available for the pilot—on-prem cluster, hybrid, or cloud burst—and do you allow external cloud bursting? Options: On-prem cluster only, On-prem + cloud allowed, Vendor-hosted cloud preferred, Cloud not permitted, Undecided
• Do you have storage performance constraints (IOPS), quota limits, or data-retention policies we should plan around? Options: No constraints, Moderate quotas, Strict quotas / low IOPS, Must archive after run, Unsure
• If compute or license shortages appear mid-pilot, what fallback is acceptable—queue to existing cluster, reduced corner set, or delayed runs? Options: Queue to cluster, Reduce corners, Delay runs, Use vendor cloud (with approval), Other

Who Owns What — and How Will We Move Fast?

• Who will be the primary owner for: data handoff, run orchestration, results triage, and executive signoff? (name/role for each)
• Which stakeholders must approve pilot scope and go/no-go decisions (select all that apply)? Options: Director, PD, VP, Eng, CFO/Finance, Foundry liaison, Legal/IP, Ops/SRE
• What cadence and format of governance do you prefer for the pilot—daily standup, weekly technical sync, and executive checkpoint? Options: Daily standup, Twice-weekly technical sync, Weekly review, Bi-weekly executive update, Ad-hoc
• If a correlation gap emerges, what's your preferred escalation path and timeline for a joint debug (e.g., 48-hour triage, 1-week engineering deep-dive)? Options: 48-hour triage, 1-week deep-dive, Immediate onsite workshop, Monthly review, Undecided
• How would you like success/failure decisions documented—pass/fail checklist, judged KPIs, or executive signoff memo? Options: Pass/fail checklist, KPI-based acceptance, Executive memo with actions, Other

How Will We Know We’ve Won (Beyond a Green Light)?

• What minimum correlation to silicon do you require to consider the pilot a technical success (e.g., mean absolute error %, percentile targets)? Options: <=1% mean absolute, <=2% mean, <=5% mean, Custom metric—describe below
• Aside from correlation, which acceptance signals matter most—runtime, foundry certification sign-off, repeatability, or engineering confidence? Options: Correlation, Runtime, Foundry certification, Repeatability, Engineer confidence
• What level of runtime improvement or predictability would justify broader rollout in your org? Options: Significant (>2x faster), Moderate (1.2–2x), Predictable same runtime, Not focused on runtime
• How much residual respin risk (probability) are you willing to tolerate post-adoption to proceed to foundry? Options: <=1% chance, <=5% chance, <=10% chance, No strict threshold—case-by-case
• Who must sign the final acceptance (name/role) and what evidence package do they require (reports, foundry letters, sample silicon comparisons)?

What Risks Are You Not Willing to Trade Away?

• Which of these risks are absolute show-stoppers for you in a pilot: IP exposure, failed foundry certification, missed tapeout date, or uncontrolled cost? Options: IP exposure, Failed foundry certification, Missed tapeout date, Uncontrolled compute costs, None are show-stoppers
• What security controls or audits do we need to agree to before any file movement (e.g., encryption, logging, SOC2, on-prem-only execution)? Options: Encryption at rest & transit, Access logging + audit, SOC2 / ISO certification, On-prem execution only, Other
• If a gap is discovered that could delay tapeout, what remediation window is acceptable (days/weeks) before escalation to executives? Options: 48–72 hours, 1 week, 2 weeks, Longer / depends
• Do you have an internal rollback or contingency plan if the pilot uncovers systemic foundry-correlation issues? Options: Yes—formal plan, Informal contingency, No plan, Unsure

Let’s Walk Through a Real Pilot Run

• Which design slice should we use as the pilot artifact—full-chip, top critical block, or representative IP block? Options: Full-chip, Top critical block, Representative IP block, Multiple blocks
• Map the ideal pilot timeline: handoff -> first-run -> debug window -> re-run -> final report. How long for each phase? Options: <1 week each, 1–2 weeks each, 2–4 weeks each, Custom—describe below
• What level of engineering enablement do your teams require for interpreting reports and debugging (guided workshop, self-serve docs, live support)? Options: Live guided workshop, On-demand docs + office hours, Self-serve documentation, Dedicated onsite support
• How granular do you expect our reports to be—block-by-block, net-level examples, or executive summaries with drill-down capability? Options: Executive + drill-down, Block-by-block with examples, Net-level case studies, All of the above
• If we hit a stubborn correlation gap, what remediation path is preferred: joint debug with your team, vendor patch, or foundry engagement? Options: Joint debug, Vendor patch, Foundry engagement, Combination

Readiness Triage — Quick Checklist and Next Steps

• If we aimed to start in two weeks, which of these items are already green: PDK access, silicon data, licenses, compute quota, signed NDA? Options: PDK access, Silicon data, Tool licenses, Compute quota, Signed NDA, None ready
• For any item not ready, what is the realistic date to have it cleared? Options: <1 week, 1–2 weeks, 2–4 weeks, 1+ months, Unknown
• What is the single best next action you can commit to this week to remove the biggest blocker?
• Who should be invited to an initial kick-off meeting to accelerate approvals and technical handoffs (list names/roles)?
• Finally, what would success in this readiness phase look like 14 days from now—list three measurable checkpoints.

Quick Intro: Where this conversation starts

• Who is the primary sponsor for signoff decisions on this tapeout? Options: Director of Physical Design, VP of Engineering, Chief Architect, Tapeout Program Manager, Other — please name
• What process node and foundry are you targeting for the upcoming tapeout? Options: 7 nm (FinFET), 5 nm, 3 nm, 3 nm+ / below, Different — please specify
• What is your current tapeout timeline (milestone for mask submission)? Options: Within 1 month, 1–3 months, 3–6 months, 6+ months, Planning stage
• Which signoff disciplines are part of your current final-gate flow? Options: Static Timing (STA), Power / IR-drop, Electromigration (EM), Physical verification / DRC/LVS, Reliability / aging checks
• How would you describe your team’s current confidence level in shipping without a respin? Options: Very confident, Somewhat confident, Wary but proceeding, Not confident at all

If this fails, what breaks first?

• If a single signoff mismatch caused a respin, what would that cost your program in schedule and dollars? Options: <$500k, $500k–$1M, $1M–$3M, $3M–$6M, >$6M / catastrophic
• Tell us about any past false-pass you experienced: what happened, which block or signoff discipline failed, and what followed?
• How often do you see divergence between your flow and foundry reference or silicon beyond your acceptance threshold? Options: Every tapeout, Often (multiple blocks), Occasionally, Rarely, Never — we haven’t validated recently
• Who in your organization ultimately accepts the residual risk to ship when correlation gaps remain? Options: Director of Physical Design, VP of Engineering, CFO/Finance, Tapeout Board / Steering Committee, Other — please specify
• When you face that trade-off, what emotions or pressures show up (e.g., fear of schedule slip, political pressure to ship)? Options: Schedule pressure, Budget constraints, Fear of reputational damage, Engineering fatigue, Other — describe

The invisible flow: how your signoff really behaves

• Which parts of your current signoff flow do you suspect are silently introducing correlation error? Options: Extraction translation errors, Corner/condition setup mismatches, Model version skew, Manual fixes and scripts, Multiple netlist conversions
• Please map your existing signoff flow end-to-end (tools, scripts, handoffs) and note any fragile handoff points.
• Which tools/vendors are involved today for extraction, STA, power, and reliability?
• How frequently do you re-run correlation after a release or PDK update? Options: Per PDK drop, Per tapeout, Ad-hoc, Rarely / never
• Where do you run into the most manual intervention—report parsing, golden comparisons, or netlist reconciliation? Options: Report parsing, Golden comparison scripts, Netlist reconciliation, Corner setup fixes, Other — explain

When accuracy and scale collide

• Which is winning today for your team: matching silicon closely, or keeping runtimes and compute costs low? Options: Accuracy first (even if slow), Balanced, Runtime / cost first, Undecided / fluctuates by project
• Describe your largest design sizes (in gates or netlist MB) and typical runtime for a full-chip MCMM signoff run.
• What compute infrastructure do you use for signoff (on-prem, cloud, hybrid)? Options: On-prem HPC, Cloud (AWS/GCP/Azure), Hybrid, Burst to cloud occasionally
• Have you experienced runtime regressions when swapping engines or updating flows on your largest designs? Options: Yes, severe, Yes, manageable, No significant regressions, Not tested at scale yet
• What runtime or capacity threshold would you require to consider a new tool acceptable for production? Options: Within 10% of current, Within 25% of current, Up to 50% slower if accuracy improves, Cannot exceed current runtime

What would 'one percent' actually change for you?

• If a new engine matched silicon within ~1% on your reference blocks, how would your go/no-go decisions change? Options: Fewer respins, Less conservative timing margins, Faster release cadence, No change until proven on multiple tapeouts
• Which correlation targets do the different stakeholders require (Director, VP, CFO)? Options: <1% Director/VPE, <2% Director/VPE, 3–5% acceptable by Finance, Other — specify per role
• For timing, power, and IR/EM, which single metric matters most to you when judging a new signoff engine? Options: Worst-case timing delta vs silicon, RMS timing error, Power percentage error, IR-drop error at hot spots, EM margin accuracy
• What respin risk tolerance would justify a tool change to your CFO (i.e., acceptable probability of respin reduction)? Options: Reduce risk by >50%, Reduce by 25–50%, Reduce by 10–25%, Anything under current level is OK
• How would you measure the financial ROI of improved correlation over the next 12 months?

The hidden roadblocks to switching

• What’s the real reason you might keep using an incumbent despite known correlation gaps? Options: Foundry certification lock, Integration cost, Training and culture, Perceived risk of new tool, Contractual / procurement hurdles
• Which integration areas worry you most when evaluating a new suite (extraction parity, netlist fidelity, reporting formats, workflows)? Options: Extraction parity, Netlist fidelity, Corner setup mapping, Report formats and automation, Toolchain hooks (APIs)
• How much engineering effort would you estimate is available for validating and migrating a pilot (FTE-weeks)? Options: <2 weeks, 2–4 weeks, 1–2 months, 2+ months
• What foundry certification or qualification steps must happen before you can consider a wider rollout? Options: Foundry letter/certification, Internal sign-off validation, Silicon-in-the-loop comparison, Third-party validation
• What non-technical barriers (procurement, legal, licensing) could slow or stop adoption?

Proof that changes stick: what evidence convinces you

• What would be the single most convincing piece of evidence that a new signoff engine is production-ready for you? Options: Tapeout-ready design correlation to silicon, Large-design runtime parity, Foundry certification, Successful phased pilot across a block
• Would you run an internal benchmark using one of your latest tapeout-ready designs as the test case? Options: Yes — full-chip, Yes — single large block, Maybe — need to discuss constraints, No
• Which success metrics must that benchmark demonstrate (pick top three)? Options: Correlation within X% vs silicon, Runtime within threshold, Memory / capacity within limits, No new false violations, Traceability to foundry models
• How would you like discrepancy governance to work during a pilot (engineering root-cause, joint war-room, escrowed bug tickets)? Options: Joint engineering triage, Escalation to product owners, Documented mitigation plan, Executive steering committee
• Who must sign off on pilot success within your org (names or roles)?

Next steps — low-risk experimentation you can do this month

• What’s the smallest pilot you’d authorize to learn fast and limit risk (scope and duration)? Options: Single block, 2–4 weeks, Full-chip trimmed corners, 4–8 weeks, Small critical path study, 1–2 weeks, Exploratory PoC only
• Which design(s) would you be willing to provision for a pilot (block, subsystem, full-chip)? Options: Single large block, Multiple blocks, Full-chip, Not ready to share designs yet
• What data access constraints or NDAs would we need to clear to proceed? Options: Standard NDA, Foundry NDA required, IT security review, No constraints
• What timeline would you expect for pilot kickoff and initial results? Options: Start within 1 week, Start within 1 month, Start within 2–3 months, TBD after internal approvals
• After the pilot, what decision outcomes would you consider acceptable (go to phased rollout, more validation, stop)? Options: Phased rollout, Additional validation with another design, Defer decision, Stop evaluation
• Any final risks, constraints, or expectations we should know about before proposing a pilot plan?