Start with the Tapeout That Kept You Up at Night

• Briefly describe the tapeout and yield shortfall that brought you here (product, process node, date, and reported % gap).
• How severe was the yield gap on that lot? Options: <2%, 2–5%, 5–10%, 10–20%, >20%
• Who first raised the issue and who is owning the remediation today? Options: Yield Engineering, Physical Design, Test/FA team, Foundry, Program/Product Manager, Other
• What did initial failure analysis point to (select all that apply) and what evidence supports that? Options: Lithography hotspots, CMP-related metal patterning, Via/misconnect issues, Process variation, Unknown / inconclusive, Other
• Which datasets from that tapeout are available right now for analysis (pick all that can be shared)? Options: GDS/OASIS, Layout views (per-block), Wafer yield maps (BIN maps), SEM/optical inspection images, Design rule reports, Failure analysis reports, None / restricted

Are You Sure 'DRC‑Clean' Isn't Hiding Problems?

• How often do designs that pass your sign‑off DRC still produce lithography/CMP-related failures in production? Options: Never, Occasionally (1–2 per year), Regularly (every tapeout), Frequently (multiple tapeouts a year), We don't track frequency well
• Describe one recent example where a DRC‑clean design produced a tricky hotspot — what pattern slipped through and why do you think it wasn't caught?
• Which analysis or DFM tools are you running today to find these problems? (select all that apply) Options: Vendor A pattern matcher, Vendor B litho-simulation, Homegrown scripts, Manual engineering review, No dedicated tool, Other
• How much engineering time is typically spent triaging tool flags per tapeout? Options: <8 hours, 8–24 hours, 1–2 weeks, 2+ weeks, Unknown
• On a scale from 1–5, how confident are you that your current flow surfaces the yield‑limiting layout patterns customers actually see on wafers? Options: 1 (Not confident), 2, 3, 4, 5 (Highly confident)

What’s Really Costing You — Not Just in Masks

• If you had to estimate the total program impact of the last hotspot incident (masks, respins, lost revenue, engineering time), which range best fits? Options: <$50k, $50k–$250k, $250k–$1M, $1M–$5M, >$5M
• How many weeks of schedule slip or delay to product launch resulted from the issue? Options: None, <2 weeks, 2–6 weeks, 6–12 weeks, >12 weeks
• How many engineers were pulled off their roadmaps to investigate and remediate? (estimate) Options: None, 1–2, 3–5, 6–10, 10+
• Tell us about the most serious downstream consequence you've seen from a missed hotspot (customer returns, wafer scrappage, late revenue recognition, etc.).
• How long has this kind of yield surprise been an intermittent or recurring issue for your team? Options: This was the first time, <1 year, 1–3 years, 3–5 years, >5 years

If Fixing Yield Was Easy, What Would Change?

• If a solution reliably identified the small subset of real yield‑killing hotspots (and cut false positives dramatically), what would your team do differently on every tapeout?
• What minimum yield improvement (%) would make this solution a clear success for you? Options: 1–2%, 2–5%, 5–10%, 10–20%, >20%
• What maximum false‑positive rate would you tolerate so engineering time savings are real? (percent of flagged items that are actionable) Options: <1%, 1–5%, 5–10%, 10–20%, >20%
• How much additional engineering time per tapeout would be acceptable to implement an integrated DFM/optimization step early in P&R? Options: None, <8 hours, 8–24 hours, 1–2 weeks, Would consider more for guaranteed yield gains
• Who must sign off that a pilot delivered 'good enough' results (roles or teams)? Options: Director of Physical Design, Yield Engineering Manager, Foundry contact, Program Manager, Test/FA lead, Other

What Would Make Teams Trust A New DFM Flow?

• Which single concern would most likely stop you from adopting a new DFM engine—accuracy, foundry acceptance, integration burden, false positives, or schedule risk? Options: Accuracy / false negatives, Too many false positives, Foundry won't accept results, Integration will delay tapeout, Cost / commercial terms, Team resistance
• Tell us about a past tool trial that failed to gain traction — what went wrong and what would you have needed to change the outcome?
• Which forms of evidence would convince you this tool is trustworthy? (select all that apply) Options: Wafer correlation/FA-backed metrics, Foundry endorsement, On-customer pilot results, Low false‑positive case studies, Open model-performance reports
• Are you willing to share wafer/inspection correlation results under NDA to enable model calibration? Options: Yes — full sharing under NDA, Partial sharing (aggregated or anonymized), No — foundry restrictions prevent sharing, Unsure — need to check
• How important is it that our tooling integrates directly into your P&R loop versus running as a post‑layout check? Options: Critical — must be in P&R, Preferable but not required, Post‑layout OK for initial trials, Undecided

Let’s Map Data & Access — The Secret Sauce

• Which of the following data types can you make available for a pilot under current agreements? (select all that apply) Options: Full GDS/OASIS, Layout per-block views, Wafer BIN/yield maps, SEM/optical images (inspection), Failure analysis reports, Process/OPC models, None / restricted
• What formats and sizes are those datasets typically in (e.g., GDS, OASIS, TIFF/PNG, CSV) and roughly how large is a representative tapeout?
• Are there foundry or customer constraints (NDAs, export controls, anonymization) that would limit model training or sharing? If so, what are they? Options: Standard NDA allows sharing, Foundry prohibits raw data export, Anonymized/aggregated sharing only, Export controls apply, Other / unsure
• Who owns or controls access to the datasets we would need (name/role)?
• How quickly could you provision a sanitized pilot dataset once the scope and NDA are agreed? Options: <1 week, 1–2 weeks, 2–4 weeks, >4 weeks, Not sure / depends

Integration Reality Check — Will This Fit Into Your Flow?

• If we needed to insert an automated DFM check into your P&R loop tomorrow, what single change would cause the most friction or schedule risk?
• Which EDA platforms and tool versions are you running that the solution must integrate with? (select all that apply) Options: Synopsys ICC/IC Compiler, Cadence Innovus, Mentor Calibre, In-house P&R, Other
• Where in your sign‑off flow would you prefer the analysis to run? (select one) Options: During early P&R (floorplan/placement), Late-stage P&R (clock closure), Post-layout signoff, Pre-mask signoff only, Hybrid — multiple stages
• What compute and security environment constraints do we need to support? (select all that apply) Options: On‑premises only, Cloud allowed (private/public), Air‑gapped environments, HPC cluster available, Limited CPU/GPU resources
• Do you have established rollback/escalation procedures for pilot changes that affect timing or layout? Briefly describe.

Deciding Together — How We Pilot and Prove Value

• If we ran a pilot on your most recent tapeout, what non‑negotiable outcomes would you need to see to consider the pilot successful? Options: Clear wafer correlation to flagged hotspots, Reduction in actionable hotspots vs current tools, Low false‑positive burden (defined threshold), Seamless integration into P&R, Foundry acceptance / sign‑off support
• What pilot scope would be most meaningful to you? Options: Full-chip analysis, Representative critical blocks only, Specific problematic layer(s) only, Multiple tapeouts for comparison, Other
• How long should a pilot run to give you confidence (pick one)? Options: 1–2 weeks, 3–4 weeks, 1–3 months, Multiple tapeouts over 6 months, Unsure
• What acceptance metrics (quantitative) will you use to decide to move from pilot to production? List the top 3 with targets (e.g., yield delta, false‑positive rate, engineering hours saved).
• Who will be accountable on your side for pilot coordination, data access, and acceptance sign‑off? Please provide role(s) and contact readiness.
• What commercial or program constraints should we be aware of when proposing a pilot (budget, legal, procurement timelines)? Options: Budget available now, Requires approval, Procurement >60 days, Legal/NDAs needed, Other / unsure

Tell Me About the Tapeout That Changed Everything

• Briefly describe the recent tapeout that triggered this review — product, process node, tapeout date, and the primary symptom you observed.
• What was the observed yield shortfall on that lot (best estimate)? Options: Less than 2%, 2–5%, 5–10%, 10–20%, More than 20%, Unknown/not yet measured
• How did failure analysis (FA) attribute the failures — which root causes were identified or suspected? Options: Lithographic hotspots, CMP-sensitive metal patterns, Etch non-uniformity, Mask defects, Design rule oversight, Other/Undetermined
• Which step in your current sign-off flow actually flagged these problems, if any? Options: DRC/LVS, Legacy DFM pattern checks, Optical proximity correction (OPC) tool, Foundry sign-off checks, None flagged, Other
• How urgent is remediation before mask commit for this project? Options: Immediate (days), 1–2 weeks, 3–4 weeks, Next tapeout, No immediate pressure / informational

Are You Comfortable Passing DRC and Calling It Done?

• What would it mean for your program if most 'DRC-pass' tapeouts routinely contained lethal hotspots your flow never called out?
• How often does a design that passed sign-off still produce post-silicon yield surprises? Options: Every tapeout, Often (majority), Occasionally, Rarely, Never
• Approximately how many yield‑limiting hotspots do you discover post-silicon per million instances on problem designs? Options: 0–50, 50–200, 200–1,000, 1,000–10,000, Unknown / not measured
• How long does it typically take your team to triage and confirm the root cause of those hotspots once FA points to them? Options: <1 week, 1–2 weeks, 2–4 weeks, 1+ months, Not tracked
• Who has final authority to delay mask commit when a suspected hotspot appears late in the flow? Options: Yield Engineering Director, Physical Design Director, Tapeout Lead, Foundry Representative, Cross-functional committee, Other

Where Are Your Tools Leaving You in the Dark?

• If your current tools are producing a flood of irrelevant flags while missing the few patterns that actually kill yield, which gap would you call the most urgent to close?
• Which EDA or DFM tools do you run today for hotspot detection and yield analysis? Options: In-house scripts, Vendor A pattern-match, Vendor B lithography sim, Foundry-provided checks, Only DRC/LVS, Other
• What types of inputs do those tools consume (select all that apply)? Options: GDS/OASIS, DEF, DRC/LVS reports, Wafer inspection images, Foundry process models/kits, No inspection/wafer linkage
• Do you currently have layout-to-wafer linked datasets (wafer hotspots mapped back to layout coordinates)? Options: Yes — routinely, Partial / occasional, No — but planning, No and not available
• How calibrated are your predictive models or rulesets to the foundry's active node and model versions? Options: Fully calibrated to current node/model, Partially calibrated, Not calibrated, Unsure
• What percentage of tool flags typically get investigated and resolved before mask commit? Options: >90%, 70–90%, 40–70%, <40%, Not tracked

What's It Actually Like When Your Team Hunts a Hotspot?

• When a suspected hotspot appears late, does your response feel like a practiced routine or a scramble? Tell me about the last time.
• Who usually performs the first-pass triage on a reported hotspot? Options: Yield Engineer, Physical Design Engineer, Design Owner/Block Lead, Foundry Engineer, Dedicated DFM Team, Other
• How do you prioritize which hotspots to fix when time is limited? Options: Estimated yield impact, Fix complexity / time to implement, Timing/critical path risk, Customer commitments / SLAs, Foundry severity rating, Other
• What data or artifacts does the triage team repeatedly ask for but rarely get in time?
• How often do candidate fixes introduce timing, power, or area regressions that force follow‑up rework? Options: Often, Occasionally, Rarely, Never, Not measured
• How does the team feel when a late hotspot forces a fix — e.g., stressed, resigned, motivated to improve the flow? Options: Stressed/anxious, Frustrated, Motivated to improve, Relieved after resolution, Other

If We Could Show You Where the Real Risk Lives...

• What would you be willing to change in your sign-off process if you were 90% confident the hotspots a new tool flagged were real yield killers and not false alarms?
• Which remediation actions would your team accept as part of sign-off remediation (select all that could be considered)? Options: Layout rework, Mask biasing/OPE adjustments, CMP-aware metal fill changes, Via geometry adjustments, Foundry process recipe changes, None without heavy validation
• What level of false positives would be tolerable for your team to adopt a new hotspot detection capability? Options: <1% of flags, 1–5%, 5–10%, 10–20%, Depends on hitlist ranking
• Conversely, what level of false negatives (missed lethal hotspots) would be unacceptable? Options: Any misses unacceptable, <1%, 1–5%, Depends on hotspot severity
• How much engineering time can you realistically allocate per tapeout to investigate flagged hotspots (per tapeout, total team effort)? Options: <8 hours, 1–2 days, 3–5 days, 1+ weeks, Flexible / depends on impact

Who Needs To Be In The Room (But Often Isn't)?

• Who has the power to veto mask commit and how often are they brought in only at the last minute?
• Which stakeholders should always be part of a pre-mask hotspot review to make a timely, practical decision? Options: Yield Engineering, Physical Design, Tapeout Lead, DFM/Tooling Owner, Foundry Representative, Test / Failure Analysis, Other
• Do you have a documented sign-off flow that includes DFM/hotspot checkpoints and who is accountable at each gate? Options: Yes — comprehensive and followed, Partial / informal, Ad hoc / verbal only, No documented flow
• How often does misalignment between stakeholders cause a hotspot to slip late into the cycle? Options: Frequently, Sometimes, Rarely, Never
• What communication cadence and channels work best for urgent decisions (email, chat, war-room, scheduled checkpoints)? Options: Email, Slack / Teams, Phone calls, Dedicated war‑room, Weekly checkpoint meeting, Ad hoc

Practical Constraints: What Reality Will Make Us Adapt?

• If we recommend P&R loop integration or sign-off server access, what are the toughest technical or organizational obstacles you expect?
• Which integration points and outputs are available today for a partner to plug into? (select all that apply) Options: Place-and-route API, DEF handoff, GDS/OASIS, Sign-off server access, Wafer inspection databases / Fab logs, None available
• What foundry model versions, PDKs, and process kits are you currently using for this tapeout?
• What data access, IP, or security constraints should we be aware of (NDA, masked IP regions, HVAs)? Options: Full access under NDA, Restricted IP segments only, Aggregated/derived metrics only, No external access permitted
• How would you like onboarding and pilot work scheduled relative to your tapeout milestones (parallel P&R, pre-signoff window, post-design review)? Options: Parallel during P&R, Dedicated pre-signoff window, Post-design verification, As-needed / flexible
• What is a realistic timeline for a pilot run on your recent tapeout (from data handoff to first hotspot report)? Options: <1 week, 1–2 weeks, 3–4 weeks, Longer than a month, Unsure

Deciding To Move: Signals, Metrics, and Acceptance

• If the pilot doesn't produce a perfect kill‑rate figure, what credible signals would still make you move forward with a solution?
• Which acceptance metrics matter most to you for pilot success? Options: Reduction in wafer fail rate (%), Reduction in high-risk hotspots flagged, False-positive reduction vs incumbent, Time-to-triage reduction, Seamless integration with P&R flow, Other
• Do you have historical wafer inspection or linked FA datasets we can use for calibration and ground-truth comparison? Options: Full linked datasets available, Partial datasets available, Summary metrics only, None available
• Would a prioritized hotspot list with estimated yield impact and suggested remediation be sufficient evidence for initial acceptance? Options: Yes, Maybe — depends on confidence level, No — we need wafer proof
• Who must sign off on pilot success and what internal timeline would they work to for a buy/no‑buy decision? Options: Yield Eng Director, Physical Design Director, Tapeout Lead, Foundry Contact, Cross-functional committee
• What practical next step would you be comfortable committing to after seeing an initial pilot report (data share, calibration meeting, integration plan)? Options: Share data and run calibration, Schedule technical deep-dive, Pilot on a second tapeout, No commitment without more proof, Other

Getting Comfortable Together

• What's the single most important reason you're exploring a pre-deployment pilot now? Options: Recent tapeout yield drop, Foundry flagged risks, Upcoming mask commit, Process node migration, Internal audit / continuous improvement, Other
• Briefly describe the tapeout, process node, and the yield gap or failure mode that triggered this conversation.
• Which foundry and process variant is this design targeting? Options: TSMC (N7/N5/N3), Samsung (N7/N5/N3), GlobalFoundries (16/12/7nm), SMIC/Other regional foundry, Confidential / can't disclose here
• What is your current timeline to mask commit or the last safe-change milestone? Options: Within 2 weeks, 2–4 weeks, 1–3 months, 3+ months, No fixed date yet
• What type of pilot engagement feels most useful to you right now? Options: Run our tools on your last tapeout and present hotspots, Integrate into P&R loop for iterative fixes, Short advisory review (no integration), Other

Who’s In the Room — and Who Can Stop the Mask?

• If a last-minute hotspot fix is proposed, who in your organization can block or delay a mask release? Options: Foundry approval, Director of Physical Design, Yield Engineering Manager, Program/Product Manager, Mask shop/MPW coordinator, Cross-functional committee
• List the decision roles, their names (or titles), and the approval gates they own for sign-off.
• Who currently owns P&R and final sign-off access (tool account owners, gatekeepers)? Options: Physical Design team, Sign-off team (separate), Foundry-managed signoff, Third-party contractor, Not yet assigned / TBD
• How quickly can those owners enact a change that affects mask data (hours, days, weeks)? Options: Within hours, 1 workday, 2–5 workdays, More than a week
• Has role confusion or handoff friction caused a missed mask window or last-minute crisis in the past? Tell us what happened.

Is Your Data Actually Usable — Or Are We Flying Blind?

• If we requested the layout and wafer/inspection data needed for a pilot today, how confident are you we'd receive everything needed within 48 hours? Options: Very confident, Somewhat confident, Possible with effort, Unlikely within 48 hours
• Which of the following datasets can you provide for the pilot? (select all that apply) Options: GDS / OASIS, DEF/LEF, Placement & routing DB, DRC/LVS logs, Foundry signoff reports, Wafer inspection images (optical), SEM / CD-SEM images, E-test logs / failing nets, Wafer map / lot history, Testchip or correlated FA reports, Process recipe / OPC settings
• Are any of these datasets restricted by NDAs, foundry agreements, or internal policy? Options: No restrictions, Company NDA required, Foundry approval required, Third-party vendor restrictions, Unknown / need to check
• What anonymization, redaction, or file-format steps must be applied before we can receive your data?
• How long has it typically taken you to gather and hand off equivalent datasets for past DFM or yield investigations? Options: Same day, 1–3 days, 1 week, 2+ weeks

Foundry Models — Ready, Outdated, or Mysterious?

• Do you trust the foundry model versions you're running against, or do you treat them as provisional until proven on silicon? Options: Trust them — silicon-calibrated, Partially trusted — some calibration gaps, Known gaps exist, We don't know the model pedigree
• Which specific foundry model versions (litho, CMP, OPC, etch) are available for this project? Please list names/versions.
• Are the models silicon-calibrated for your process and the layers of interest? Options: Yes — silicon-calibrated, Partially calibrated, No — reference-only, Unknown
• If a model gap exists, who is responsible for obtaining, validating, or calibrating the correct model (internal team, foundry contact, vendor)? Options: Internal PD team, Yield/FA team, Foundry liaison, Third-party service, Shared responsibility
• Would your foundry permit us to use their calibrated models for a pilot under NDA? Options: Yes — permitted, Yes — with approvals, No — not permitted, Unknown

Tooling, Access, and Integration — Are the Doors Open?

• How deeply can we integrate with your P&R and sign-off flow for the pilot — full in-loop, periodic handoff, or strictly post-route analysis? Options: Full in-loop integration, Periodic handoff (e.g., nightly), Post-route only (advisory), No integration permitted
• Which place-and-route and sign-off tools (and versions) do you use? Options: Cadence Innovus, Synopsys ICC2, Synopsys Fusion, Mentor (Calibre/others), OpenROAD / custom flows, Other
• Can our tooling run inside your environment (on-prem) or must we operate on our infrastructure with secure upload? Options: On-prem integration allowed, Only secure upload to our infra, Both options possible, Not decided
• Who will provide engineering owners for integration and remediation steps, and how many FTEs can be allocated during the pilot? Options: 0 (we expect vendor to run), 0.2–0.5 FTE, 1–2 FTEs, 3+ FTEs, TBD
• Do you have CI/CD, automated flow scripts, or SRE support we should know about when integrating? Options: Yes — mature automation, Partial automation, Manual flows only, Unknown

If Things Go Wrong — Who Pulls the Emergency Cord?

• If a remediation change introduces a timing or functional regression, what is your typical response and who owns the rollback decision? Options: PD team rolls back immediately, Cross-functional review required, Escalate to program manager/foundry, No formal rollback process — ad hoc
• Do you have a documented rollback plan for mask changes or quick-patch procedures? If yes, briefly summarize.
• What escalation path do you expect during a pilot for critical issues (names/titles and expected response times)?
• Have you ever executed an emergency rollback or stopped a mask release due to DFM/FA findings? What happened and what would you change next time?
• What maximum acceptable response time (SLA) would you expect from our team for critical pilot issues? Options: Within 1 hour, Within 4 hours, Within 1 business day, Within 2–3 business days

How We'll Measure Success — The Acceptance Checklist

• Are you more concerned about minimizing false positives that waste engineering time — or maximizing detection of any possible hotspot even at the cost of noise? Options: Minimize false positives (conservative), Maximize detection (aggressive), Balanced — predefined thresholds, Undecided / need guidance
• Which of the following will be formal acceptance gates for the pilot? (select all that apply) Options: Detected real hotspots correlated to FA, False-positive rate below X%, Measured yield improvement on pilot lots, Fix implementation effort under Y engineering hours, No timing/functional regressions post-fix, Foundry signoff on pilot changes
• How will wafer/inspection validation be provided and what is the expected turnaround (e.g., next wafer, 2–3 weeks)? Options: Next wafer (fast), Next lot (2–3 weeks), Post-run analysis (4+ weeks), No immediate wafer validation planned
• Who formally signs off that the pilot met acceptance criteria (titles/roles)? Options: Director, Physical Design, Yield Engineering Manager, Foundry liaison, Program Manager, Cross-functional committee
• What would cause you to declare the pilot unsuccessful even if some metrics improved?

Practical Next Steps — From Agreement to First Run

• What would make you comfortable committing to a 4–6 week pilot starting as early as next month? Options: Clear data-share NDA, Foundry model availability, Dedicated PD/Yield FTEs, Executive sponsorship, No blockers — ready to go
• List the immediate blockers to starting the pilot and the person or team responsible for each blocker.
• Which legal / contracting items do we need to complete before data transfer (company NDA, foundry waiver, MSA, other)? Options: Company NDA, Foundry approval/waiver, Data processing agreement, MSA or SOW, None / already in place
• Propose an ideal kickoff date and a realistic fallback date for the pilot. Options: Immediately, 1–2 weeks, 2–4 weeks, 1–2 months, More than 2 months
• Who should be our day-to-day contact for coordination (name/title/email) and who is the executive sponsor we should keep informed?
• Is there anything else about your environment, constraints, or past experiences that would help us design a low-risk, high-value pilot?

Quick Intro: Who You Are & Which Tapeout We're Looking At

• Who is the primary contact we should work with on manufacturability and yield for this engagement? Options: Director of Physical Design, Yield Engineering Manager, VP Engineering, Team Lead - Physical Design, Foundry Liaison, Other
• What was the date (or planned date) of the recent tapeout you want us to evaluate?
• Briefly summarize the observed yield shortfall from that lot (%, when observed, one-sentence root cause if known).
• Which internal and external teams would participate in a pilot or remediation (pick all that apply)? Options: Physical Design (PD), Yield Engineering (YE), Failure Analysis (FA), Foundry Liaison, Fab/Wafer Ops, Procurement/Legal, Other
• Do you already have layout and wafer/inspection data immediately available for analysis? Options: Full layout + wafer inspection data available, Partial data available (samples or summaries), Only layout available, No, we need time to collect

If DRC Says 'Pass', Why Are Wafers Saying 'Fail'?

• Have you been treating a 'DRC-clean' signoff as a guarantee, even when wafer results suggest otherwise? Options: Yes — historically trusted DRC as sufficient, Sometimes — depends on the project, No — we've always expected extra DFM checks, Unsure
• When yield failed recently, what concrete evidence pointed to lithography or CMP-sensitive patterns rather than electrical bugs?
• How many tapeouts in the last 12 months showed unexpected yield issues traced back to pattern-related manufacturing problems? Options: None, 1, 2-3, 4-6, 7+
• What emotional or business consequences did that yield shortfall cause (e.g., schedule slips, executive escalations, lost revenue)?
• What would it feel like for your team if these pattern-driven yield losses stopped happening?

Where Your Current Signoff Flow Hides Noise

• Which hidden checks or manual steps in your signoff flow are most likely masking real yield risk?
• Which tools and checks compose your current signoff flow (select all that apply)? Options: Native DRC (Calibre/Hercules), Third-party DFM pattern matcher, In-house heuristics/scripts, ML-based hotspot detection, P&R-integrated checks, Manual FA review / visual inspection, Other
• Where in the flow does DFM typically run for your projects? Options: Pre-P&R (floorplan/architecture), During P&R loop, Post-P&R, pre-signoff, After signoff (late catch), Varies by project
• How much engineering time do you normally allocate to reviewing and triaging DFM/DFT findings per tapeout? Options: < 1 week, 1–2 weeks, 2–4 weeks, 4+ weeks
• Walk me through a recent example where a flagged issue was deprioritized and later traced to yield impact—what happened and why?

Are Your Tools Raising the Right Alarm or Just Noise?

• If your current toolset is flagging tens of thousands of patterns while only a few hundred actually kill yield, how long can your team keep sorting noise from signal? Options: We can manage it today, It's becoming unsustainable, It's actively harming schedules, Unsure
• Approximately how many DFM/DFT findings does your current flow produce per million layout features (choose closest)? Options: <1k, 1k–10k, 10k–50k, 50k–200k, 200k+
• Based on failure analysis, how many true yield-killing hotspots did you find per recent tapeout (estimate)? Options: 0, 1–10, 11–50, 51–200, 200+
• Which root causes have actually shown up in wafer failures for you (select all that applied)? Options: Lithography hotspot (CD/LER issues), CMP-sensitive metal patterns, Via/connection opens, Etch non-uniformity, Overlay/registration, Optical proximity errors, Other
• How many engineering-hours does it typically take to triage and validate a single flagged hotspot from your current flow? Options: <1 hour, 1–4 hours, 4–12 hours, 12–40 hours, 40+ hours
• What would reducing false positives by an order of magnitude enable your team to do differently in the run-up to mask commit?

How Confident Are You in Your Foundry Models and Calibration?

• How confident are you that your foundry PDKs and process models reflect the real wafer behavior you’re seeing? Options: Highly confident, Somewhat confident, Low confidence, We don't have visibility
• Which process nodes are most relevant for this evaluation (select all that apply)? Options: 28nm, 14nm, 10nm, 7nm, 5nm, 3nm, Other
• Has your DFM/hotspot engine been calibrated against your wafer inspection data before? Options: Calibrated to wafer inspection data, Partially calibrated, Not calibrated, Unknown
• If calibration is partial or missing, roughly how much wafer data would you expect is needed to get to production-grade accuracy (samples, lots, or wafers)?
• Would you be willing to share wafer inspection files and corresponding layout for calibration under NDA / data controls? Options: Yes — full data under NDA, Yes — but only anonymized/sampled data, Only summaries/metrics, No — cannot share

What Does 'Good Enough' for Acceptance Actually Mean?

• If we deliver a prioritized remediation list, what single metric would make you call the pilot a success? Options: % yield improvement, Reduction in false positives, Foundry acceptance/signoff, Time saved in review, Number of critical hotspots eliminated, Other
• What minimum yield improvement (percentage points) would justify the engineering effort and any delay to mask commit? Options: <1%, 1–3%, 3–5%, 5–10%, 10%+
• What false-positive target would you consider acceptable for a production-ready hotspot detector (per million flagged)? Options: <50, 50–200, 200–1000, 1000+
• Who needs to sign off on acceptance—internal owners and any foundry stakeholders—and what form must acceptance take?
• How do you prefer the acceptance evidence to be presented: quantified hotspot list + wafer correlation, visual overlays on GDS, or sample-focused FA cases? Options: Quantified list + wafer correlation, Visual overlays on GDS/OASIS, FA case studies with images, All of the above, Other

Who Will Do the Work — Integration, Fixes, and Operational Ownership?

• When the tool hands over prioritized fixes, who will be responsible for implementing them? Options: Physical Design Engineers, Yield Engineers, Dedicated DFM Team, Foundry Engineering, Outsourced contractors, Other
• How tolerant is your timing window for fixes that may require re-timing or ECOs? Options: No tolerance — cannot change timing, Small tolerance — minor ECOs allowed, Moderate tolerance — schedule can flex, High tolerance — we can absorb delays
• Which EDA and P&R tools must the solution integrate with (select all that apply)? Options: Synopsys ICC2, Cadence Innovus, Mentor Calibre, Foundry signoff tools, Custom scripts/APIs, Data lake / wafer DB, Other
• What enablement format do your engineers respond to best when adopting a new tool? Options: Hands-on workshops, Recorded training, Office hours support, Dedicated enablement engineer, Self-serve docs
• Do you want the DFM analysis embedded into the P&R loop (catch early) or run as a high-confidence post-P&R gate? Options: Embedded in P&R loop, High-confidence post-P&R gate, Both (phased), Undecided

What’s Really Holding Back Adoption—Beyond Technology

• If a technology reduced false positives by 100x, what non-technical reason might still make your team resist adoption?
• Have you seen cultural or organizational blockers when trying to add another sign-off step? If so, what were they?
• What procurement, licensing, or foundry approval hurdles do we need to anticipate for a pilot and subsequent rollout?
• How emotionally ready is your team to try a new DFM approach right now? Options: Very open / eager, Cautiously open, Neutral, Reluctant / defensive
• What would most reduce resistance—clear ROI, foundry endorsement, low-risk pilot terms, or a dedicated integrator? Options: Clear ROI, Foundry endorsement, Low-risk pilot terms, Dedicated integrator/engineer, Other

Pilot Practicalities: Data, Legal, and Timeline

• Will you allow an external model to run against your recent layout and wafer data for a pilot, assuming standard NDAs? Options: Yes — full access under NDA, Yes — anonymized/sampled data only, Only summary metrics, No — cannot allow external runs
• Which data artifacts can you provide for the pilot (choose all that apply)? Options: GDSII/OASIS layout, DEF/LEF, LVS/netlist, Wafer inspection images (SEM/optical), Metrology logs (CD, overlay), Foundry PDK/model files, Other
• What legal or foundry approvals (NDAs, partner agreements) are required before data can be shared? Options: Existing corporate NDA sufficient, Need foundry/partner NDA, Require anonymization + legal review, Cannot share without executive approval
• What timeline would you be looking for a pilot from data handoff to actionable remediation list? Options: 2 weeks, 4 weeks, 6–8 weeks, 3 months, Unsure
• What would success look like in the first pilot report (specific deliverables you expect)?

If We Showed Yield Recovery, How Quickly Could You Commit?

• If a pilot demonstrated a prioritized set of fixes that recovered X% yield, how quickly could you commit to executing them? Options: Immediately, Within 2 weeks, Within 1 month, 1–3 months, Need executive approval
• Who holds final budget or escalation authority for a pilot and subsequent purchase? Options: I control budget, I influence decision; procurement controls, Procurement/Contracts, Executive approval required, Other
• What commercial model would make a pilot low-friction for you? Options: No-cost pilot with evaluation, Paid pilot, Subscription trial, Pilot bundled into enterprise contract, Other
• Which stakeholders must be present for a kickoff meeting to make a pilot productive? Options: PD lead, YE lead, FA lead, Foundry liaison, Tooling/IT owner, Procurement/Legal
• What communication cadence do you prefer during a pilot (to keep momentum but not overwhelm teams)? Options: Weekly sync, Bi-weekly, As-needed, Daily during critical windows, Monthly

Final Check: Concerns, Red Flags, and Small Commitments

• What would be an immediate red flag that would stop you from moving forward after the pilot?
• Are there any internal deadlines, regulatory windows, or foundry mask-commit gates we must not interfere with?
• What is one small, non-disruptive thing we could do in the next 7–14 days to build trust with your team? Options: Show anonymized example correlation to wafer, Run a quick scan on a small layout subset, Provide a short tech deep-dive for engineers, Share customer case studies with similar nodes, Other
• Who should we follow up with next and what is the preferred channel to schedule the kickoff? Options: Email, Calendar invite, Slack/Teams, Phone